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<title>u-boot.git/arch/powerpc/include, branch v2024.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2023-05-31T18:05:34Z</updated>
<entry>
<title>powerpc: use asm-generic/unaligned.h</title>
<updated>2023-05-31T18:05:34Z</updated>
<author>
<name>Jens Wiklander</name>
<email>jens.wiklander@linaro.org</email>
</author>
<published>2023-05-22T12:22:35Z</published>
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<id>urn:sha1:5b70e460c967c67c2cda16303f7bd965cfa6137f</id>
<content type='text'>
Powerpc configurations are apparently able to do unaligned accesses. But
in an attempt to clean up and handle unaligned accesses in the same way
we ignore that and use the common asm-generic/unaligned.h directly
instead.

Signed-off-by: Jens Wiklander &lt;jens.wiklander@linaro.org&gt;
Reviewed-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
</content>
</entry>
<entry>
<title>include: Remove unused header files</title>
<updated>2023-05-31T16:31:47Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-05-16T16:34:47Z</published>
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<id>urn:sha1:f1671205fa44084b334027a267c86e5be2ea7c1a</id>
<content type='text'>
As part of various code clean-ups we have on occasion missed removing
unused header files.  None of these files are referenced anywhere else
at this point.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc885: Add CPM USB-SOF microcode for CPM15 ERRATA</title>
<updated>2023-05-05T05:26:53Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-05-03T06:50:55Z</published>
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<id>urn:sha1:62c5fae511494590e6b8404c315fe156575a0753</id>
<content type='text'>
MPC885 CPU has the following ERRATA:

	When the USB controller is configured in Host mode, and the
	SOF generation (SFTE=1 in USMOD register) is being used,
	there may be false CRC error indication in other SCCs.
	Although the data is received correctly, the CRC result
	will be corrupted.

Add capability to load the related microcode to fix it.
The microcode binary data is copied from Linux kernel.

Other microcode will be added in following patch so make it
a Kconfig choice.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>powerpc: Force cast on memcpy_toio()</title>
<updated>2023-05-05T05:26:53Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-05-05T05:24:16Z</published>
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<id>urn:sha1:3febc89563f69494e69c04b30ffbed04fa3c2b82</id>
<content type='text'>
sparse reports the following warning:

  CHECK   arch/powerpc/cpu/mpc8xx/micropatch_usb_sof.c
arch/powerpc/cpu/mpc8xx/micropatch_usb_sof.c:29:9: warning: cast removes address space '&lt;asn:2&gt;' of expression
arch/powerpc/cpu/mpc8xx/micropatch_usb_sof.c:30:9: warning: cast removes address space '&lt;asn:2&gt;' of expression

This is because of (void *) casts for using memcpy() as a substitute.

Do like other architectures, __force the cast to silence the warning

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc8xx: Reorganise init RAM</title>
<updated>2023-05-04T10:40:47Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-05-04T08:20:35Z</published>
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<id>urn:sha1:bebb8dfabc3af9eeca4283000571a7400cb88c71</id>
<content type='text'>
Using SMC relocation microcode patch or USB-SOF microcode patch
will disable DPRAM memory from 0x2000 to 0x2400 and from 0x2f00
to 0x3000.

At the time being, init RAM is setup to use 0x2800-0x2e00, but
the stack pointer goes beyond 0x2800 and even beyond 0x2400.

For the time being we are not going to use any microcode patch
that uses memory about 0x3000, so reorganise setup to use:
- 0x2800 - 0x2e00 for init malloc and global data and CPM buffers
- 0x3000 - 0x3c00 for init stack

For more details about CPM dual port ram, see
commit b1d62424cb ("powerpc: mpc8xx: redistribute data in CPM dpram")

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc8xx: CPM parameter RAM can be anywhere</title>
<updated>2023-05-04T08:58:07Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-05-03T08:31:19Z</published>
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<id>urn:sha1:fdd243d81bcf5e7fdc8cc7b5060c0c6ed60c5c81</id>
<content type='text'>
With relocation, CPM parameter RAM can be anywhere in the
dual port RAM, so don't split dual port RAM.

Remove dparam and dparam16 members of struct comm_proc

PROFF_XXX become offsets from the start of dual port RAM,
then they are now consistant with the offsets in RPBASE
registers.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>spi: mpc8xxx: Add support for SPI on mpc832x</title>
<updated>2023-04-06T12:50:03Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-03-02T15:26:26Z</published>
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<id>urn:sha1:83945efacff3ee4ed15457b2b9b627aab9814eba</id>
<content type='text'>
On mpc832x, SPI can be either handled by CPU or QE.
In order to work in CPU mode, bit 17 of SPMODE has to
be set to 1, that bit is called OP.

Also, data is located at a different place than the one expected
by the driver today. In 8 bits mode with REV set, data to be
transmitted is located in the most significant byte while
received data is located in second byte. So perform the
necessary shifts.

In order to differentiate with other CPUs, a new compatible is
added for mpc832x: fsl,mpc832x-spi

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
Cc: Rasmus Villemoes &lt;rasmus.villemoes@prevas.dk&gt;
</content>
</entry>
<entry>
<title>gpio: Add QUICC Engine GPIOs driver</title>
<updated>2023-04-06T12:50:03Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-02-21T18:31:11Z</published>
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<id>urn:sha1:e1fff66079d29ef59521771cf0aaa5ac4a834b50</id>
<content type='text'>
The mpc832x has GPIOs handled by the QUICC Engine.
The registers are different from the one for the
non QE mpc83xx GPIOs.

Implement a GPIO driver for those.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc83xx: Fix soc.h</title>
<updated>2023-04-06T12:50:03Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-04-04T13:09:18Z</published>
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<id>urn:sha1:8886a819615eac220aba1de77b996a6da0b68155</id>
<content type='text'>
There are helpers included in soc.h

Declare them static inline so that soc.h can be
included in several places.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>driver, gpio: Add support for MPC 8xx CPU ports</title>
<updated>2023-02-11T07:47:58Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2022-10-14T08:01:41Z</published>
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<id>urn:sha1:02239394988d363b65234be9f7ca75f864e523b3</id>
<content type='text'>
Ports A, C and D are 16 bits ports.
Ports B and E are 32 bits ports.

The "compatible" is used to determine each port type.

This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
Reviewed-by: FRANJOU Stephane &lt;stephane.franjou@csgroup.eu&gt;
</content>
</entry>
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