u-boot.git/arch/powerpc, branch v2011.03 Unnamed repository; edit this file 'description' to name the repository. powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs 2011-03-29T12:41:37+00:00 Prabhakar Kushwaha prabhakar@freescale.com 2011-02-01T15:55:58+00:00 b03a466d6ceb9dbfd1a1638f355e9c8b4833259f The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe.  Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
powerpc/85xx: Enable various errata on P1022/P1013 SoCs 2011-03-28T14:04:26+00:00 Jiang Yutang b14898@freescale.com 2011-01-30T23:06:20+00:00 2d7534a344412409d03e4a341614e4320c48879b Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on P1022/P1013 SoCs. Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2. Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on
P1022/P1013 SoCs.

Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2.

Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Merge branch 'master' of git://git.denx.de/u-boot-arm 2011-03-27T19:20:29+00:00 Wolfgang Denk wd@denx.de 2011-03-27T19:20:29+00:00 c04bf5e9a45d7335681352faa125193258f8e976 






rename _end to __bss_end__
2011-03-27T17:18:37+00:00

Po-Yu Chuang
ratbert@faraday-tech.com

2011-03-01T22:59:59+00:00

44c6e6591cb451ae606f8bde71dd5fb7b4002544

Currently, _end is used for end of BSS section.  We want _end to mean
end of u-boot image, so we rename _end to __bss_end__ first.

Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>





Currently, _end is used for end of BSS section.  We want _end to mean
end of u-boot image, so we rename _end to __bss_end__ first.

Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>







powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134
2011-03-24T14:20:50+00:00

York Sun
yorksun@freescale.com

2011-03-17T18:18:13+00:00

eb672e92f44a5e3c1780c74ded073727d2887434

The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>





The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>







powerpc/mpc8xxx: disable rcw_en bit for non-DDR3
2011-03-24T14:20:50+00:00

York Sun
yorksun@freescale.com

2011-03-17T18:18:12+00:00

4ca31929466b2804eac74d04ec7bf656c568250e

rcw_en bit is only available for DDR3 controllers. It is a reserved bit on
DDR1 and DDR2 controllers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>





rcw_en bit is only available for DDR3 controllers. It is a reserved bit on
DDR1 and DDR2 controllers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>







powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address Parity
2011-03-24T14:20:49+00:00

York Sun
yorksun@freescale.com

2011-03-17T18:18:10+00:00

08b3f7599f7bdf7e96cf46ecb9eecffc92b323d2

To recognize DIMMs with ECC capability by testing ECC bit only. Not to be
confused by Address Parity bit.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>





To recognize DIMMs with ECC capability by testing ECC bit only. Not to be
confused by Address Parity bit.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>







Introduce a new linker flag LDFLAGS_FINAL
2011-03-22T22:32:06+00:00

Haiying Wang
Haiying.Wang@freescale.com

2011-02-22T21:38:05+00:00

6dc1eceb9c5f42216f1ba0e0ef538015b0aa10bc

commit 8aba9dceebb14144e07d19593111ee3a999c37fc
Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS

breaks the usage of --gc-section to build nand_spl. We still need linker option
--gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes
the --gc-sections to each uboot image.

To get the proper linker flags, we use LDFLAGS and LDFLAGS_FINAL to replace
PLATFORM_LDFLAGS in the Makefile of each nand_spl board.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>





commit 8aba9dceebb14144e07d19593111ee3a999c37fc
Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS

breaks the usage of --gc-section to build nand_spl. We still need linker option
--gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes
the --gc-sections to each uboot image.

To get the proper linker flags, we use LDFLAGS and LDFLAGS_FINAL to replace
PLATFORM_LDFLAGS in the Makefile of each nand_spl board.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>







powerpc/85xx: Fix synchronization of timebase on MP boot
2011-03-15T06:25:51+00:00

Kumar Gala
galak@kernel.crashing.org

2011-03-13T15:55:53+00:00

7afc45ad7d9493208d89072cbb78a5bfc8034b59

There is a small ordering issue in the master core in that we need to
make sure the disabling of the timebase in the SoC is visible before we
set the value to 0.  We can simply just read back the value to
synchronizatize the write, before we set TB to 0.

Reported-by: Dan Hettena
Tested-by: Dan Hettena
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>





There is a small ordering issue in the master core in that we need to
make sure the disabling of the timebase in the SoC is visible before we
set the value to 0.  We can simply just read back the value to
synchronizatize the write, before we set TB to 0.

Reported-by: Dan Hettena
Tested-by: Dan Hettena
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>







mpc8[5/6]xx: Ensure POST word does not get reset
2011-03-13T16:24:44+00:00

John Schmoller
jschmoller@xes-inc.com

2011-03-10T22:09:26+00:00

cc1dd33f273f8c96cbd7539b4a2d1d7aa12773cd

The POST word is stored in a spare register in the PIC on MPC8[5/6]xx
processors.  When interrupt_init() is called, this register gets reset
which resulted in all POST_RAM POSTs not being ran due to the corrupted
POST word.  To resolve this, store off POST word before the PIC is
reset, and restore it after the PIC has been initialized.

Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>





The POST word is stored in a spare register in the PIC on MPC8[5/6]xx
processors.  When interrupt_init() is called, this register gets reset
which resulted in all POST_RAM POSTs not being ran due to the corrupted
POST word.  To resolve this, store off POST word before the PIC is
reset, and restore it after the PIC has been initialized.

Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>