We assumed that only a small set of compatiable strings would be needed to find the PCIe device tree nodes to be fixed up. However on newer platforms the simple rules no longer work. We need to allow specifying the PCIe compatiable string for each individual SoC. We introduce CONFIG_SYS_FSL_PCIE_COMPAT for this purpose and set it if the default isn't sufficient. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Reword "The DIMM max tCKmin is ..." to "The DDR clock is faster than the slowest DIMM(s) can support". Fixed interger type in printf as well. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The compatible property for the L2 cache node (on 85xx systems that don't have a CPC) was using a value for the property length that did not match the actual length of the property. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated 4/27/11) states that rev D processors may wake up with the wrong feature set. This patch implements the APM-proposed workaround. To enable this patch for your board, add the appropriate define for your CPU to your board header file. See kilauea.h for more information. The following variants are supported: #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY Please note that if you select the wrong define, your board will not boot, and JTAG will be required to recover. Tested on custom boards using: CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY <sfalco@harris.com> CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY <eibach@gdsys.de> Signed-off-by: Steve Falco <sfalco@harris.com> Acked-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
Currently, some linker scripts are found by common code in config.mk. Some are found using CONFIG_SYS_LDSCRIPT, but the code for that is sometimes in arch config.mk and sometimes in board config.mk. Some are found using an arch-specific rule for looking in CPUDIR, etc. Further, the powerpc config.mk rule relied on CONFIG_NAND_SPL when it really wanted CONFIG_NAND_U_BOOT -- which covered up the fact that not all NAND_U_BOOT builds actually wanted CPUDIR/u-boot-nand.lds. Replace all of this -- except for a handful of boards that are actually selecting a linker script in a unique way -- with centralized ldscript finding. If board code specifies LDSCRIPT, that will be used. Otherwise, if CONFIG_SYS_LDSCRIPT is specified, that will be used. If neither of these are specified, then the central config.mk will check for the existence of the following, in order: $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT) $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT) $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds $(TOPDIR)/$(CPUDIR)/u-boot.lds Some boards (sc3, cm5200, munices) provided their own u-boot.lds that were dead code, because they were overridden by a CPUDIR u-boot.lds under the old powerpc rules. These boards' own u-boot.lds have bitrotted and no longer work -- these lds files have been removed. Signed-off-by: Scott Wood <scottwood@freescale.com> Tested-by: Graeme Russ <graeme.russ@gmail.com>
- serial console on UART1 - Ethernet RMII over UCC4 - PHY SMSC LAN8700 - 64MB Flash - 128 MB DDR2 RAM - I2C - bootcount This board is similiar to the kmeter1 (8360) board, so common config options are extracted into the include/configs/km83xx-common.h file. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> cc: Kim Phillips <kim.phillips@freescale.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>