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<title>u-boot.git/arch/powerpc, branch v2014.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc?h=v2014.04</id>
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<updated>2014-04-02T10:25:01Z</updated>
<entry>
<title>mmc:eSDHC: Workaround for data timeout issue on Txxx SoC</title>
<updated>2014-04-02T10:25:01Z</updated>
<author>
<name>Haijun.Zhang</name>
<email>Haijun.Zhang@freescale.com</email>
</author>
<published>2014-03-18T09:04:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1336e2d343f088b71ec71907855caccd1053d166'/>
<id>urn:sha1:1336e2d343f088b71ec71907855caccd1053d166</id>
<content type='text'>
1. The Data timeout counter value in eSDHC_SYSCTL register is
not working as it should be, so add quirks to enable this
workaround to fix it to the max value 0xE.

2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround.

* Update of patch for change mmc interface by
	Pantelis Antoniou &lt;panto@antoniou-consulting.com&gt;

Signed-off-by: Haijun Zhang &lt;Haijun.Zhang@freescale.com&gt;
Acked-by: Pantelis Antoniou &lt;panto@antoniou-consulting.com&gt;
</content>
</entry>
<entry>
<title>kbuild: rename OBJTREE to objtree</title>
<updated>2014-03-12T21:04:58Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-03-11T02:05:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5ee828ca95de622cd11d0f3ddcccf97f4935de5b'/>
<id>urn:sha1:5ee828ca95de622cd11d0f3ddcccf97f4935de5b</id>
<content type='text'>
Prior to Kbuild, $(OBJTREE) was used for pointing to the
top of build directory with absolute path.

In Kbuild style, $(objtree) is used instead.
This commit renames OBJTREE to objtree and delete the
defition of OBJTREE.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
</entry>
<entry>
<title>kbuild: rename TOPDIR to stctree</title>
<updated>2014-03-12T21:04:55Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-03-11T02:05:19Z</published>
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<id>urn:sha1:4379ac614809da2128f8bc1f62e3dde4daaf7deb</id>
<content type='text'>
Prior to Kbuild, $(TOPDIR) or $(SRCTREE) was used for
pointing to the top of source directory.
(No difference between the two.)

In Kbuild style, $(srctree) is used instead.
This commit renames TOPDIR to srctree and delete the
defition of TOPDIR.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
</entry>
<entry>
<title>usb: create common header virtual root hub descriptors</title>
<updated>2014-03-10T17:53:36Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@wwwdotorg.org</email>
</author>
<published>2014-02-14T04:15:18Z</published>
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<id>urn:sha1:eb838e7d84a5211ccca0662297b4dfd1cc29e9df</id>
<content type='text'>
Many USB host controller drivers contain almost identical copies of the
same virtual root hub descriptors. Put these into a common file to avoid
duplication.

Note that there were some very minor differences between the descriptors
in the various files, such as:

- USB 1.0 vs. USB 1.1
- Manufacturer/Device ID
- Max packet size
- String content

I assume these aren't relevant.

Cc: Thomas Lange &lt;thomas@corelatus.se&gt;
Cc: Shinya Kuribayashi &lt;skuribay@pobox.com&gt;
Cc: Gary Jennejohn &lt;garyj@denx.de&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Eric Millbrandt &lt;emillbrandt@coldhaus.com&gt;
Cc: Pierre Aubert &lt;p.aubert@staubli.com&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Daniel Hellstrom &lt;daniel@gaisler.com&gt;
Cc: Denis Peter &lt;d.peter@mpl.ch&gt;
Cc: Rodolfo Giometti &lt;giometti@linux.it&gt;
Cc: Zhang Wei &lt;wei.zhang@freescale.com&gt;
Cc: Mateusz Zalega &lt;m.zalega@samsung.com&gt;
Cc: Remy Bohmer &lt;linux@bohmer.net&gt;
Cc: Markus Klotzbuecher &lt;mk@denx.de&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Cc: Gary Jennejohn &lt;garyj@denx.de&gt;
Cc: C Nauman &lt;cnauman@diagraph.com&gt;
Cc: David Müller &lt;d.mueller@elsoft.ch&gt;
Cc: Yoshihiro Shimoda &lt;shimoda.yoshihiro@renesas.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
Cc: Thomas Abraham &lt;t-abraham@ti.com&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Andrew Murray &lt;amurray@embedded-bits.co.uk&gt;
Cc: Matej Frančeškin &lt;matej.franceskin@comtrade.com&gt;
Cc: Cliff Cai &lt;cliff.cai@analog.com&gt;
Cc: Bryan Wu &lt;cooloney@gmail.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx</title>
<updated>2014-03-08T01:54:22Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2014-03-08T01:54:22Z</published>
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<id>urn:sha1:247161b8160fc699b0a517f081220bb50bc502a8</id>
<content type='text'>
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040</title>
<updated>2014-03-07T22:53:29Z</updated>
<author>
<name>Priyanka Jain</name>
<email>Priyanka.Jain@freescale.com</email>
</author>
<published>2014-01-30T10:09:58Z</published>
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<id>urn:sha1:bf4699db852f88b0a30b9d7e8b1bea83d01c0d92</id>
<content type='text'>
T1040 SoC has SCFG (Supplement Configuration) Block which provides
chip specific configuration and status support. The base address of
SCFG block in T1040 is 0xfc000.
SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register)
at offset 0x28.

Add definition of
-SCFG block
-SCFG_PIXCLKCR register
-Bits definition of SCFG_PIXCLK register

Signed-off-by: Priyanka Jain &lt;Priyanka.Jain@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>bootstage: powerpc: support fdt stash and reporting</title>
<updated>2014-03-07T22:52:31Z</updated>
<author>
<name>Mela Custodio</name>
<email>sessyargc@gmail.com</email>
</author>
<published>2014-02-19T15:16:57Z</published>
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<id>urn:sha1:b892465dae6afc5528724c044991a76f241cd177</id>
<content type='text'>
This implements stashing of bootstage timing data to FDT and automatic
timing reporting. To enable define CONFIG_BOOTSTAGE_FDT and
CONFIG_BOOTSTAGE_REPORT respectively.

Signed-off-by: Rommel G Custodio &lt;sessyargc+u-boot@gmail.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/usb: Workaround for erratum-A006261</title>
<updated>2014-03-07T22:52:16Z</updated>
<author>
<name>Suresh Gupta</name>
<email>suresh.gupta@freescale.com</email>
</author>
<published>2014-02-26T08:59:12Z</published>
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<id>urn:sha1:9c641a872aa54edc97d69281f705819e96a5c90e</id>
<content type='text'>
USB spec says that the minimum disconnect threshold should be
	over 525 mV. However, internal USB PHY threshold value is below
	this specified value. Due to this some devices disconnect at
	run-time. Hence, phy settings are tweaked to increased disconnect
	threshold to be above 525mV by using this workaround.

Signed-off-by: Suresh Gupta &lt;suresh.gupta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/b4860: Add workaround for errata A006384 and A006475</title>
<updated>2014-03-07T22:52:01Z</updated>
<author>
<name>Shaveta Leekha</name>
<email>shaveta@freescale.com</email>
</author>
<published>2014-02-26T10:38:22Z</published>
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<id>urn:sha1:7af9a07403e80415d097b4175616c7a7686b7deb</id>
<content type='text'>
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configuration

Both these errata are only applicable for b4 rev1.
So, make workaround for these errata conditional,
depending upon soc version.

Signed-off-by: Shaveta Leekha &lt;shaveta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>B4860/B4420: Add PLL_NUM define for B4420/B4860 to use SerDes2 Refclks re-configuration</title>
<updated>2014-03-07T22:50:10Z</updated>
<author>
<name>Shaveta Leekha</name>
<email>shaveta@freescale.com</email>
</author>
<published>2014-02-26T10:37:37Z</published>
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<id>urn:sha1:6df82e3c0f3e1b160ff08dbf4a2e36f8c75de68e</id>
<content type='text'>
B4860 has two PLL per SerDes whereas B4420 has one PLL per SerDes,
add their defines in arch/powerpc/include/asm/config_mpc85xx.h

Signed-off-by: Shaveta Leekha &lt;shaveta@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
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