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<title>u-boot.git/arch/powerpc, branch v2016.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc?h=v2016.07</id>
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<updated>2016-07-05T15:40:28Z</updated>
<entry>
<title>powerpc: mpc85xx: Do not build errata command in SPL</title>
<updated>2016-07-05T15:40:28Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-07-05T15:40:27Z</published>
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<id>urn:sha1:12c67d7522d77c5aa5ee1e5ec4147b569ccb7666</id>
<content type='text'>
The errata command is useless in SPL, so don't build it. This fixes
multiple build failures on PowerPC.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: York Sun &lt;york.sun@nxp.com&gt;
Fixes: 92623672f9d3 ("fsl: usb: make errata function common for PPC and ARM")
</content>
</entry>
<entry>
<title>Remove unneeded remnants of bcopy().</title>
<updated>2016-06-06T17:39:18Z</updated>
<author>
<name>Robert P. J. Day</name>
<email>rpjday@crashcourse.ca</email>
</author>
<published>2016-05-30T10:55:53Z</published>
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<id>urn:sha1:25bab53ab26efdb9e2024477f896be65b6e7191e</id>
<content type='text'>
Since bcopy() is no longer used, delete all remaining references to
it.

Signed-off-by: Robert P. J. Day &lt;rpjday@crashcourse.ca&gt;
</content>
</entry>
<entry>
<title>dm: gpio: Add driver for MPC85XX GPIO controller</title>
<updated>2016-06-04T05:13:24Z</updated>
<author>
<name>mario.six@gdsys.cc</name>
<email>mario.six@gdsys.cc</email>
</author>
<published>2016-05-25T13:15:20Z</published>
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<id>urn:sha1:07d31f8f98fb350776c78a681ef27fd8ee288acd</id>
<content type='text'>
This patch adds a driver for the built-in GPIO controller of the MPC85XX
SoC (probably supporting other PowerQUICC III SoCs as well).

Each GPIO bank is identified by its own entry in the device tree, i.e.

gpio-controller@fc00 {
      #gpio-cells = &lt;2&gt;;
      compatible = "fsl,pq3-gpio";
      reg = &lt;0xfc00 0x100&gt;
}

By default, each bank is assumed to have 32 GPIOs, but the ngpios
setting is honored, so the number of GPIOs for each bank in configurable
to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of
the P1022 SoC).

The usual functions of GPIO drivers (setting input/output mode and output
value setting) are supported.

The driver has been tested on MPC85XX, but it is likely that other
PowerQUICC III devices will work as well.

Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>arch/powerpc: Simplify some calculations using ARRAY_SIZE() macro.</title>
<updated>2016-06-04T05:13:12Z</updated>
<author>
<name>Robert P. J. Day</name>
<email>rpjday@crashcourse.ca</email>
</author>
<published>2016-05-23T10:49:21Z</published>
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<id>urn:sha1:b7707b043ebbf88fe0fb49442db9316ded3a0740</id>
<content type='text'>
Replace a number of array length calculations with the ARRAY_SIZE()
macro, for clarity.

Signed-off-by: Robert P. J. Day &lt;rpjday@crashcourse.ca&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>Delete tests of CONFIG_OF_LIBFDT when testing CONFIG_OF_BOARD_SETUP</title>
<updated>2016-05-27T19:41:16Z</updated>
<author>
<name>Robert P. J. Day</name>
<email>rpjday@crashcourse.ca</email>
</author>
<published>2016-05-19T19:23:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7ffe3cd62e5af2cda1e18c6d896cab58bfb0c811'/>
<id>urn:sha1:7ffe3cd62e5af2cda1e18c6d896cab58bfb0c811</id>
<content type='text'>
Since CONFIG_OF_BOARD_SETUP depends on CONFIG_OF_LIBFDT:

  config OF_BOARD_SETUP
          bool "Set up board-specific details in device tree before boot"
          depends on OF_LIBFDT
          ...

remove superfluous tests of CONFIG_OF_LIBFDT when testing for
CONFIG_OF_BOARD_SETUP.

Signed-off-by: Robert P. J. Day &lt;rpjday@crashcourse.ca&gt;
[trini: Typo fix: s/ifdefi/ifdef/]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>powerpc: Drop unused code related to generic board</title>
<updated>2016-05-27T19:39:54Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-15T00:49:34Z</published>
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<id>urn:sha1:14c67ebaefec6d477603454aa2998c36da40453b</id>
<content type='text'>
Since generic board init is enabled, this is not used. Drop it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx</title>
<updated>2016-05-25T11:19:31Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-05-25T11:19:31Z</published>
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<id>urn:sha1:826d06dbdd0e29ab0d8bd76d1ca640e2dfdb076c</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2016-05-24T17:42:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-05-24T17:42:03Z</published>
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<id>urn:sha1:fc15b9beed05dec6cc092c265042381a0eadb0e9</id>
<content type='text'>
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache</title>
<updated>2016-05-24T17:31:21Z</updated>
<author>
<name>Aneesh Bansal</name>
<email>aneesh.bansal@nxp.com</email>
</author>
<published>2016-04-18T17:28:33Z</published>
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<id>urn:sha1:82eda68444fa4d026bcf1f59c7c0d044ddbcb193</id>
<content type='text'>
While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.

Signed-off-by: Aneesh Bansal &lt;aneesh.bansal@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>powerpc: Disable flush or invalidate dcache by range for some SoCs</title>
<updated>2016-05-19T17:47:11Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-04-07T16:56:48Z</published>
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<id>urn:sha1:cb1629f91a487e34284868a2d246bc3b122c6395</id>
<content type='text'>
Commit ac337168a unified functions to flush and invalidate dcache by
range. These two functions were no-op for SoCs other than 4xx and
MPC86xx. Adding these functions seemed to be correct but introduced
issues when the dcache is flushed. While the root cause is under
investigation, disable these functions for affected SoCs so various
drivers can work.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
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