u-boot.git/arch/powerpc, branch v2016.09

net: mii: Changes not made by spatch

2016-08-15T20:29:03+00:00

If the functions passed to the registration function are not in the same
C file (extern) then spatch will not handle the dependent changes.

Make those changes manually.

Signed-off-by: Joe Hershberger 

For the 4xx related files:
Acked-by: Stefan Roese 
Reviewed-by: Bin Meng

net: mii: Fix changes made by spatch

2016-08-15T20:29:03+00:00

Some of the changes were a bit too complex.

Signed-off-by: Joe Hershberger 
Reviewed-by: Bin Meng

net: mii: Use spatch to update miiphy_register

2016-08-15T20:26:33+00:00

Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base.

Signed-off-by: Joe Hershberger 
Reviewed-by: Bin Meng

ppc4xx: Fix platform support

2016-08-09T07:25:36+00:00

Commit "ecc3066 Fix board init code to respect the C runtime environment"
broke platform support for ppc4xx.
start.S prepares a stackframe that is later rendered unusable by appending
the reserved space for global data.
Instead the reserved space has to be put first. Then the stackframe can
be pushed.

I can only test the 405EP OCM case. At least all other ppc4xx boards still
build.

Signed-off-by: Dirk Eibach 
Signed-off-by: Stefan Roese

treewide: move CONFIG_PHYS_64BIT to Kconfig

2016-08-05T11:27:25+00:00

We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so
that it is always available to the build system.  Otherwise we can run
into cases where we have inconsistent sizes of certain attributes.

Ravi Babu reported offset mismatch of struct dwc3 across files since
commit 95ebc253e6d4 ("types.h: move and redefine resource_size_t").
Since the commit, resource_addr_t points to phys_addr_t, whose size
is dependent on CONFIG_PHYS_64BIT for ARM architecture.

I tried my best to use "select" where possible (for example, ARMv8
architecture) because I think this kind of option is generally user-
unconfigurable.  However, I see some of PowerPC boards have 36BIT
defconfigs as well as 32BIT ones.  I moved CONFIG_PHYS_64BIT to the
defconfigs for such boards.

CONFIG_36BIT is no longer referenced, so all of the defines were
removed from CONFIG_SYS_EXTRA_OPTIONS.

Fixes: 95ebc253e6d4 ("types.h: move and redefine resource_size_t")
Signed-off-by: Masahiro Yamada 
Reported-by: Ravi Babu 
Acked-by: Stefan Roese 
Reviewed-by: Tom Rini 
Reviewed-by: York Sun

powerpc/mpc85xx: Update erratum workaround for A006379

2016-08-02T16:43:13+00:00

Update erratum workaround for A006379 to set register CPCHDBCR0
with value 0x001e0000, replacing the old value 0x003c0000.

Signed-off-by: York Sun 
Reported-by: Dave Liu

Merge git://git.denx.de/u-boot-mpc86xx

2016-07-26T21:34:51+00:00

SECURE_BOOT: Enable SD as a source for bootscript

2016-07-26T16:01:43+00:00

Add support for reading bootscript and bootscript header from SD. Also
renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and
NOR flash.

Reviewed-by: Aneesh Bansal 
Signed-off-by: Sumit Garg 
Reviewed-by: Simon Glass 
Reviewed-by: York Sun

powerpc/86xx: Pass -mcpu=7400 to GCC

2016-07-25T19:51:16+00:00

Without this, GCC uses the toolchain default, which may be incompatible
with -maltivec.

Signed-off-by: Scott Wood 
Reviewed-by: York Sun

powerpc/mpc85xx: T104x: Add nand secure boot target

2016-07-21T18:09:34+00:00

For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configured as SRAM. But in case of secure boot, this default address
always maps to IBR (Internal Boot ROM).
The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G
address space i.e. 0x0 - 0xDFFFFFFF.

For secure boot target from NAND, the text base for SPL is kept same as
non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will
be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000)
As a the virtual and physical address of CPC would be different. The
virtual address 0xFFFx_xxxx needs to be mapped to physical address
0xBFFx_xxxx.

Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000
and update DCFG SCRTACH1 register with location of Header required for
secure boot.

The changes are similar to
commit 467a40dfe35f48d830f01a72617207d03ca85b4d
    powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC
is only 256K and thus SPL framework is used.
The changes are only applicable for SPL U-Boot running out of CPC SRAM
and not the next level U-Boot loaded on DDR.

Reviewed-by: Ruchika Gupta 
Reviewed-by: Simon Glass 
Signed-off-by: Aneesh Bansal 
Signed-off-by: Sumit Garg 
Reviewed-by: York Sun