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<title>u-boot.git/arch/powerpc, branch v2023.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2023-05-07T13:44:27Z</updated>
<entry>
<title>Merge branch 'for-2023.07-2' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx</title>
<updated>2023-05-07T13:44:27Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-05-07T13:44:27Z</published>
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<id>urn:sha1:1917a1a8a8bad28170cd464e5ea61ff0d738310b</id>
<content type='text'>
This pull request adds misc fixes for cssi boards and activates
CPM relocation in order to enable the use of SCC4 in
QMC (QUICC Multi-Channel) mode.
</content>
</entry>
<entry>
<title>powerpc: mpc8xx: Add SMC relocation CPM microcode</title>
<updated>2023-05-05T05:26:53Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-05-03T06:57:33Z</published>
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<id>urn:sha1:e7930e93cc6f8d442a86feeaa4c77332a875b02f</id>
<content type='text'>
In order to use QMC mode in the CPM, a SCC requires more space
in parameter RAM.

After SCC1 there is I2C parameter RAM and after SCC2 there is
SPI parameter RAM. MPC866 and MPC885 can already relocate I2C and.
SPI parameter RAM.

But in order to free space after SCC3 and SCC4, SMC1 and SMC2
need to be relocated. In order to do so, a CPM microcode patch
is required.

Binary data for that patch is copied from Linux kernel.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc885: Add CPM USB-SOF microcode for CPM15 ERRATA</title>
<updated>2023-05-05T05:26:53Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-05-03T06:50:55Z</published>
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<id>urn:sha1:62c5fae511494590e6b8404c315fe156575a0753</id>
<content type='text'>
MPC885 CPU has the following ERRATA:

	When the USB controller is configured in Host mode, and the
	SOF generation (SFTE=1 in USMOD register) is being used,
	there may be false CRC error indication in other SCCs.
	Although the data is received correctly, the CRC result
	will be corrupted.

Add capability to load the related microcode to fix it.
The microcode binary data is copied from Linux kernel.

Other microcode will be added in following patch so make it
a Kconfig choice.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>powerpc: Force cast on memcpy_toio()</title>
<updated>2023-05-05T05:26:53Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-05-05T05:24:16Z</published>
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<id>urn:sha1:3febc89563f69494e69c04b30ffbed04fa3c2b82</id>
<content type='text'>
sparse reports the following warning:

  CHECK   arch/powerpc/cpu/mpc8xx/micropatch_usb_sof.c
arch/powerpc/cpu/mpc8xx/micropatch_usb_sof.c:29:9: warning: cast removes address space '&lt;asn:2&gt;' of expression
arch/powerpc/cpu/mpc8xx/micropatch_usb_sof.c:30:9: warning: cast removes address space '&lt;asn:2&gt;' of expression

This is because of (void *) casts for using memcpy() as a substitute.

Do like other architectures, __force the cast to silence the warning

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc8xx: Reorganise init RAM</title>
<updated>2023-05-04T10:40:47Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-05-04T08:20:35Z</published>
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<id>urn:sha1:bebb8dfabc3af9eeca4283000571a7400cb88c71</id>
<content type='text'>
Using SMC relocation microcode patch or USB-SOF microcode patch
will disable DPRAM memory from 0x2000 to 0x2400 and from 0x2f00
to 0x3000.

At the time being, init RAM is setup to use 0x2800-0x2e00, but
the stack pointer goes beyond 0x2800 and even beyond 0x2400.

For the time being we are not going to use any microcode patch
that uses memory about 0x3000, so reorganise setup to use:
- 0x2800 - 0x2e00 for init malloc and global data and CPM buffers
- 0x3000 - 0x3c00 for init stack

For more details about CPM dual port ram, see
commit b1d62424cb ("powerpc: mpc8xx: redistribute data in CPM dpram")

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc8xx: CPM parameter RAM can be anywhere</title>
<updated>2023-05-04T08:58:07Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-05-03T08:31:19Z</published>
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<id>urn:sha1:fdd243d81bcf5e7fdc8cc7b5060c0c6ed60c5c81</id>
<content type='text'>
With relocation, CPM parameter RAM can be anywhere in the
dual port RAM, so don't split dual port RAM.

Remove dparam and dparam16 members of struct comm_proc

PROFF_XXX become offsets from the start of dual port RAM,
then they are now consistant with the offsets in RPBASE
registers.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>mpc83xx: Don't allow W and G bits in IBATs</title>
<updated>2023-05-01T22:59:33Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-01-27T13:51:06Z</published>
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<id>urn:sha1:f1dc0daf7a7c73e525d52698ab914b8f833bed00</id>
<content type='text'>
The "Programming Environments Manual for 32-Bit Implementations of the
PowerPC™ Architecture" says "W and G bits are not defined for IBAT
registers. Attempting to write to these bits causes boundedly-undefined
results"

The "e300 Power Architecture™ Core Family Reference Manual" says the
same: "Neither the W or G bits of the IBAT registers should be set.
Attempting to write to these bits causes boundedly-undefined results."

Remove the possibility to set those bytes.

Fixes: 30915ab95d9 ("mpc83xx: Migrate BATS config to Kconfig")
Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
Cc: Mario Six &lt;mario.six@gdsys.cc&gt;
</content>
</entry>
<entry>
<title>Merge branch 'for-2023.07' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx</title>
<updated>2023-04-29T13:29:41Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-04-29T13:29:41Z</published>
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<id>urn:sha1:fe3a77cb157a6210d8036845f5f80ea67c183563</id>
<content type='text'>
This pull request adds support for the last CPU board from
CS GROUP France (previously CSSI).

That CPU board called CMPCPRO has a mpc8321E CPU (Family PQII PRO hence
its name) and can be plugged in place of the CMPC885 board.

In order to support that new board, the following changes are included
in this series:
- Make the mpc8xx watchdog driver more generic for reusing it
with mpc83xx
- Fix various small problems on mpc83xx platform
- Add a GPIO Driver for QE GPIOs
- Add support for mpc832x into mpc83xx SPI driver
- Refactor existing board code that will be shared with new board
- Add the new board
</content>
</entry>
<entry>
<title>board: cssi: Add CPU board CMPCPRO</title>
<updated>2023-04-28T15:52:23Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2023-04-04T11:09:36Z</published>
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<id>urn:sha1:4d0c8db74d83e43dec4e7481b2d1e194f51d907b</id>
<content type='text'>
CSSI has another CPU board, similar to the CMPC885 board
that get plugged on the two base boards MCR3000_2G and MIAE.

That CPU board is called CMPCPRO because it has a MPC8321E CPU,
also known as Power QUICC II PRO.

Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>mpc8379erdb: Convert to using DM_SERIAL</title>
<updated>2023-04-25T19:31:28Z</updated>
<author>
<name>Sinan Akman</name>
<email>sinan@writeme.com</email>
</author>
<published>2023-04-07T22:03:44Z</published>
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<id>urn:sha1:23fd87c489276050b229b469c0cba4cb0e9d7a59</id>
<content type='text'>
  Convert to DM_SERIAL for mpc8379erdb.

Signed-off-by: Sinan Akman &lt;sinan@writeme.com&gt;
</content>
</entry>
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