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<title>u-boot.git/arch/powerpc, branch v2025.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/powerpc?h=v2025.07</id>
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<updated>2025-03-14T15:31:36Z</updated>
<entry>
<title>Merge tag 'mmu-next-14032025' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next</title>
<updated>2025-03-14T15:31:36Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-03-14T15:31:36Z</published>
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<id>urn:sha1:973c366ce68d9a99e16bcbce3941a1c52492c097</id>
<content type='text'>
Up to now we configure the entire memory space for U-Boot as RWX.
For modern architectures and security requirements, it's better to
map the memory properly.
This pull request adds basics support for mapping the U-Boot binary with
proper (RO, RW, RW^X) memory permissions on aarch64 right after we
relocate U-Boot in the top of DRAM.
It's worrth noting that the linker script annotations are only added for
the aarch64 architecture. We can, in the future, try to unify the linker --
at least for the architectures that have enough in common and expand this
</content>
</entry>
<entry>
<title>treewide: Add a function to change page permissions</title>
<updated>2025-03-14T11:37:54Z</updated>
<author>
<name>Ilias Apalodimas</name>
<email>ilias.apalodimas@linaro.org</email>
</author>
<published>2025-02-20T13:54:42Z</published>
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<id>urn:sha1:ec1c6cfb1cfce92909a248f10c36bd8b18894d7e</id>
<content type='text'>
For armv8 we are adding proper page permissions for the relocated U-Boot
binary. Add a weak function that can be used across architectures to change
the page permissions

Tested-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt; # on AML-S905X-CC
Signed-off-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: fsl_esdhc: Migrate ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE to Kconfig</title>
<updated>2025-03-13T18:15:50Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-02-27T15:29:42Z</published>
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<id>urn:sha1:569dceef2e57c76c9439ea9eb8ca6019cedf7c5d</id>
<content type='text'>
The flag for enabling the ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE quirk can be
handled easily enough in Kconfig. This lets us remove a function but not
obviously correct usage of the IS_ENABLED() macro.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "Misc. PowerPC MPC83xx fixes/cleanups"</title>
<updated>2024-12-30T21:55:33Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-12-30T21:55:33Z</published>
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<id>urn:sha1:ad09ccf7fea365e380d7c7c74e9b87b4c09f30ce</id>
<content type='text'>
J. Neuschäfer &lt;j.ne@posteo.net&gt; says:

This patchset contains a few small fixes/cleanups for the MPC83xx
platform.

Link: https://lore.kernel.org/r/20241220-mpc83xx-misc-v2-0-ff4c17ee5fa4@posteo.net
</content>
</entry>
<entry>
<title>powerpc: mpc83xx: Use defined constant for SPCR[TBEN]</title>
<updated>2024-12-30T21:55:27Z</updated>
<author>
<name>J. Neuschäfer</name>
<email>j.ne@posteo.net</email>
</author>
<published>2024-12-20T10:37:53Z</published>
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<id>urn:sha1:ba26b1d0fb923c0b145f15d132dc7561267bb8a9</id>
<content type='text'>
To increase readability, use the defined constant instead of specifying
SPCR[TBEN] as a number.

Reviewed-by: Sinan Akman &lt;sinan@writeme.com&gt;
Signed-off-by: J. Neuschäfer &lt;j.ne@posteo.net&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc83xx: Allow including initreg.h into multiple files</title>
<updated>2024-12-30T21:55:27Z</updated>
<author>
<name>J. Neuschäfer</name>
<email>j.ne@posteo.net</email>
</author>
<published>2024-12-20T10:37:52Z</published>
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<id>urn:sha1:b3e8c67a91b6e614fa84db270010da4faa702a42</id>
<content type='text'>
Globals defined in headers can result in multiple-definition errors
while linking, if they are visible beyond the current translation unit.

This hasn't been a problem for initreg.h so far, but would become a
problem in the next patch, where I use a constant from initreg.h in a
second C file.

Reviewed-by: Sinan Akman &lt;sinan@writeme.com&gt;
Signed-off-by: J. Neuschäfer &lt;j.ne@posteo.net&gt;
</content>
</entry>
<entry>
<title>Merge patch series "powerpc: Fix and enforce distinction between immediates and registers"</title>
<updated>2024-12-30T21:55:11Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-12-30T21:55:11Z</published>
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<id>urn:sha1:c379590ab7eaabc00c21eb49796d99627d33ac97</id>
<content type='text'>
J. Neuschäfer &lt;j.ne@posteo.net&gt; says:

This patchset changes the definition r0 etc. to %r0, so that the
assembler can check that registers are only used where expected, and
fixes the fallout.

Link: https://lore.kernel.org/r/20241212-gpr-checks-v1-0-8c084c5fc0b6@posteo.net
</content>
</entry>
<entry>
<title>powerpc: Introduce and enforce assembler checks on GPR usage</title>
<updated>2024-12-30T21:55:07Z</updated>
<author>
<name>J. Neuschäfer</name>
<email>j.ne@posteo.net</email>
</author>
<published>2024-12-12T17:05:47Z</published>
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<id>urn:sha1:c3e425ead43b9d6c387673f0c09100535584b038</id>
<content type='text'>
PowerPC general-purpose registers are historically specified as plain
numbers (0-31), which makes them hard to distinguish from immediates.
For this reason, include/ppc_asm.tmpl defines aliases named r0-r31.
This can still lead to uncaught mistakes if a register is used in place
of a number.

Instead of (e.g.) 5 use %r5, which will result in an assembler warning
if used as a number. Turn these warnings into errors by passing
`--fatal-warnings` to the assembler.

I verified with gazerbeam_defconfig (MPC83xx) and qemu-ppce500_defconfig
(MPC85xx) that this patch results in the same machine code.

Signed-off-by: J. Neuschäfer &lt;j.ne@posteo.net&gt;
</content>
</entry>
<entry>
<title>powerpc: Fix 0 vs. r0 confusion in X/D-form instructions</title>
<updated>2024-12-30T21:55:07Z</updated>
<author>
<name>J. Neuschäfer</name>
<email>j.ne@posteo.net</email>
</author>
<published>2024-12-12T17:05:46Z</published>
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<id>urn:sha1:fd1c2938c0ef23db322b974a5d2b8020aa6a8750</id>
<content type='text'>
Instructions such as dcbi are in the X-form; they have RA and RB fields
and the effective address (EA) is computed as (RA|0)+(RB). In words,
this means that if RA is zero, the left-hand side of the addition is
zero, otherwise the corresponding GPR is used. r0 can never be used on
the left-hand side of a X-form instruction.

For D-form instructions such as addis, the Power ISA illustrates this in
the instruction pseudo-code:

	if RA = 0 then RT &lt;-        EXTS(SI || 0x0000)
	else           RT &lt;- (RA) + EXIS(SI || 0x0000)

In all of these cases, RA=0 indicates the value zero, not register r0.

I verified with gazerbeam_defconfig (MPC83xx) and qemu-ppce500_defconfig
(MPC85xx) that this patch results in the same machine code.

Signed-off-by: J. Neuschäfer &lt;j.ne@posteo.net&gt;
</content>
</entry>
<entry>
<title>lmb: Remove lmb_reserve_flags()</title>
<updated>2024-12-30T19:21:55Z</updated>
<author>
<name>Ilias Apalodimas</name>
<email>ilias.apalodimas@linaro.org</email>
</author>
<published>2024-12-18T07:02:32Z</published>
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<id>urn:sha1:900a8951c3b6035c25632438ebc7240cbc77883c</id>
<content type='text'>
lmb_reserve() is just calling lmb_reserve_flags() with LMB_NONE.
There's not much we gain from this abstraction.
So let's remove the latter, add the flags argument to lmb_reserve()
and make the code a bit easier to follow.

Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Tested-by: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Signed-off-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
</content>
</entry>
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