u-boot.git/arch/riscv/Makefile, branch master

riscv: Add Kconfig options to distinguish Zaamo and Zalrsc

2025-09-19T11:22:29+00:00

Ratified on Apr. 2024, the original RISC-V "A" extension is now split
into two separate extensions, "Zaamo" for atomic operations and "Zalrsc"
for load-reserved/store-conditional instructions.

For now, we've already seen real-world designs implement the Zalrsc
extension only[2]. As U-Boot mainly runs with only one HART, we could
easily support these designs by not using AMO instructions in the
hard-written assembly if necessary, for which this patch introduces two
new Kconfig options to indicate the availability of "Zaamo" and "Zalrsc".

Note that even with this patch, "A" extension is specified in the ISA
string passed to the compiler as long as one of "Zaamo" or "Zalrsc" is
available, since they're only recognized with a quite recent version of
GCC/Clang. The compiler usually doesn't automatically generate atomic
instructions unless the source explicitly instructs it to do so, thus
this should be safe.

Link: https://github.com/riscv/riscv-zaamo-zalrsc/commit/d94c64c63e9120d56bdeb540caf2e5dae60a8126 # [1]
Link: https://lore.kernel.org/u-boot/20250729162035.209849-9-uros.stajic@htecgroup.com/ # [2]
Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

Kbuild: Always use $(PHASE_)

2025-04-11T18:16:44+00:00

It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our
Makefiles as part of the macros to determine when to do something in our
Makefiles based on what phase of the build we are in. For consistency,
bring this down to a single macro and use "$(PHASE_)" only.

Signed-off-by: Tom Rini

global: Rename SPL_ to XPL_

2024-10-11T17:44:48+00:00

Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is
no-longer set.

Signed-off-by: Simon Glass

riscv: add backtrace support

2024-04-09T03:29:38+00:00

When debugging, it is useful to have a backtrace to find
out what is in the call stack as the previous function (RA)
may not have been the culprit.

Since this adds size to the build, do not add it by default
and avoid putting it in the SPL build if not needed.

Signed-off-by: Ben Dooks 
Tested-by: Leo Yu-Chi Liang

riscv: Add Zbb support for building U-Boot

2023-10-19T09:29:50+00:00

This patch adds ISA string to the -march to generate zbb instructions
for U-Boot binaries, along with optimized string functions introduced
from Linux kernel.

Signed-off-by: Yu Chien Peter Lin 
Reviewed-by: Leo Yu-Chi Liang

riscv: support building double-float modules

2022-10-20T07:22:21+00:00

The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a
compiled for double-float. To link to it we have to adjust how we build
U-Boot.

As U-Boot actually does not use floating point at all this should not
make a significant difference for the produced binaries.

Signed-off-by: Heinrich Schuchardt 
Reviewed-by: Rick Chen 
Reviewed-by: Leo Yu-Chi Liang

riscv: Fix build against binutils 2.38

2022-10-07T12:42:51+00:00

The following description is copied from the equivalent patch for the
Linux Kernel proposed by Aurelien Jarno:

>From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I` extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction,
this causes the following build failure:

arch/riscv/cpu/mtrap.S: Assembler messages:
arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'

Signed-off-by: Alexandre Ghiti 
Reviewed-by: Bin Meng 
Tested-by: Heinrich Schuchardt 
Tested-by: Heiko Stuebner 
Tested-by: Christian Stewart 
Reviewed-by: Rick Chen

riscv: add Kconfig entries for the code model

2018-12-18T01:56:26+00:00

RISC-V has two code models, medium low (medlow) and medium any (medany).
Medlow limits addressable memory to a single 2 GiB range between the
absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory
to any single 2 GiB address range.

By default, medlow is selected for U-Boot on both 32-bit and 64-bit
systems.

The -mcmodel compiler flag is selected according to the Kconfig
configuration.

Signed-off-by: Lukas Auer 
[bmeng: adjust to make medlow the default code model for U-Boot]
Signed-off-by: Bin Meng 
Reviewed-by: Anup Patel

riscv: set -march and -mabi based on the Kconfig configuration

2018-11-26T05:57:29+00:00

Use the new Kconfig entries to construct the ISA string for the -march
compiler flag. The -mabi compiler flag is selected based on the base
integer instruction set.

With this change, the C (compressed instructions) ISA extension is now
enabled for all boards with CONFIG_RISCV_ISA_C set. Buildman reports a
decrease in binary size of 71590 bytes.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng

riscv: Make start.S available for all targets

2018-10-03T09:48:14+00:00

Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.

Signed-off-by: Bin Meng 
Reviewed-by: Lukas Auer