u-boot.git/arch/riscv/cpu/Makefile, branch master Unnamed repository; edit this file 'description' to name the repository. riscv: Move trap handler codes to mtrap.S 2018-12-18T01:56:27+00:00 Bin Meng bmeng.cn@gmail.com 2018-12-12T14:12:41+00:00 4b3f5ed5ac1a4376c29c3010d25049c03de4ed57 Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 
Currently the M-mode trap handler codes are in start.S. For future
extension, move them to a separate file mtrap.S.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
riscv: Make start.S available for all targets 2018-10-03T09:48:14+00:00 Bin Meng bmeng.cn@gmail.com 2018-09-26T13:55:17+00:00 b5369c5813aa407139fc137ccbd0944190f15ebc Currently start.S is inside arch/riscv/cpu/ax25/, but it can be common for all RISC-V targets. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> 
Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
riscv: Add a helper routine to print CPU information 2018-10-03T09:47:55+00:00 Bin Meng bmeng.cn@gmail.com 2018-09-26T13:55:14+00:00 2fab2e9c88c4ceba9156411474b8cfceadeb61fa This adds a helper routine to print CPU information. Currently it prints all the instruction set extensions that the processor core supports. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> 
This adds a helper routine to print CPU information. Currently
it prints all the instruction set extensions that the processor
core supports.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>