u-boot.git/arch/riscv/cpu/ax25/cache.c, branch master

riscv: Rename Andes cpu and board names

2023-02-17T11:07:48+00:00

The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.

Signed-off-by: Leo Yu-Chi Liang 
Reviewed-by: Yu Chien Peter Lin 
Reviewed-by: Rick Chen

riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL

2023-02-17T11:07:48+00:00

This patch refines L1 cache enable/disable and v5l2-cache enable
functions.

Signed-off-by: Yu Chien Peter Lin 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Rick Chen

riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"

2023-02-17T11:07:48+00:00

There is no need for RISCV_NDS_CACHE config to control cache switches.

Signed-off-by: Leo Yu-Chi Liang 
Reviewed-by: Yu Chien Peter Lin 
Reviewed-by: Rick Chen

common: Drop net.h from common header

2020-05-18T21:33:31+00:00

Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.

Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.

Signed-off-by: Simon Glass

riscv: ax25: cache: Remove SPL_RISCV_MMODE config check

2020-04-23T02:13:23+00:00

CONFIG_IS_ENABLED(FOO) will check FOO config option for U-Boot,
SPL and TPL, so remove unnecessary CONFIG_IS_ENABLED()

Signed-off-by: Pragnesh Patel 
Reviewed-by: Bin Meng

riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

2019-12-10T00:23:10+00:00

The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao

common: Move some cache and MMU functions out of common.h

2019-12-02T23:23:55+00:00

These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.

Move them over.

Signed-off-by: Simon Glass 
Reviewed-by: Tom Rini

riscv: cache: use CCTL to flush d-cache

2019-09-03T01:31:03+00:00

Use CCTL command to do d-cache write back
and invalidate instead of fence.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng

riscv: cache: Flush L2 cache before jump to linux

2019-09-03T01:31:03+00:00

Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.

The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng

CONFIG_SPL_SYS_[DI]CACHE_OFF: add

2019-05-18T12:15:35+00:00

While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.

Acked-by: Alexey Brodkin 
Signed-off-by: Trevor Woerner 
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini