u-boot.git/arch/riscv/cpu/ax25/cpu.c, branch main

riscv: Rename Andes cpu and board names

2023-02-17T11:07:48Z

The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Rick Chen

riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()

2023-02-17T11:07:48Z

As the OpenSBI v1.2 does not enable the cache [0], we enable the i/d-cache in harts_early_init() and do not disable in cleanup_before_linux(). This patch also simplifies the logic and moves the CSR encoding to include/asm/arch-andes/csr.h. [0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen

riscv: ae350: Enable CCTL_SUEN

2023-02-01T08:17:34Z

CCTL operations are available to Supervisor/User-mode software under the control of the mcache_ctl.CCTL_SUEN control bit. Enable it to support Supervisor(and User) CCTL operations. Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang

riscv: ae350: enable Coherence Manager for ae350

2021-10-07T08:08:23Z

If Coherence Manager were not set in the beginning, u-boot-spl would sometimes fail to boot to u-boot proper. Enable CM and I/D cache at the same time in harts_early_init Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen

common: Move ARM cache operations out of common.h

2019-12-02T23:24:58Z

These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass Reviewed-by: Daniel Schwierzeck Reviewed-by: Tom Rini

common: Move some cache and MMU functions out of common.h

2019-12-02T23:23:55Z

These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass Reviewed-by: Tom Rini

riscv: cache: Implement i/dcache [status, enable, disable]

2018-11-26T05:58:01Z

AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen Cc: Greentime Hu

riscv: Move do_reset() to a common place

2018-10-03T09:48:43Z

We don't have a reset method on any RISC-V board yet. Instead of adding the same 'unsupported' message for each CPU variant it might make more sense to add a generic do_reset function for all CPU variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c). Suggested-by: Lukas Auer Signed-off-by: Bin Meng Reviewed-by: Lukas Auer

riscv: cpu: nx25: Rename as ax25

2018-05-29T06:45:02Z

Andes has rearranged the product combinations. nx25 and ax25 both are RISC-V architecture cpu core. But ax25 has MMU unit inside, and nx25 is not. Cpu nx25 and platform ae250 are arranged in pairs. Cpu ax25 and platform ae350 are arranged in pairs. This patch will rename nx25 as ax25 ae250 as ae350 nx25-ae250 as ax25-ae350 including filename, variable, string and definition. Then u-boot can boot linux kernel in ae350 platform reasonably. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu