u-boot.git/arch/riscv/cpu/ax25, branch master

riscv: Rename Andes cpu and board names

2023-02-17T11:07:48Z

The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Rick Chen

configs: ae350: Enable v5l2 cache for AE350 platforms in SPL

2023-02-17T11:07:48Z

To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit: ca06444aac2c643db3a3f2eb37afc60fae15177e Turing on does not significantly increase the size of u-boot-spl.bin, so we enable it by default to improve performance. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen

riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL

2023-02-17T11:07:48Z

This patch refines L1 cache enable/disable and v5l2-cache enable functions. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen

riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()

2023-02-17T11:07:48Z

As the OpenSBI v1.2 does not enable the cache [0], we enable the i/d-cache in harts_early_init() and do not disable in cleanup_before_linux(). This patch also simplifies the logic and moves the CSR encoding to include/asm/arch-andes/csr.h. [0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen

riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"

2023-02-17T11:07:48Z

There is no need for RISCV_NDS_CACHE config to control cache switches. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Rick Chen

riscv: ax25: bypass malloc when spl fit boots from ram

2023-02-01T08:17:45Z

When fit image boots from ram, the payload will be prepared in the address of SPL_LOAD_FIT_ADDRESS. In spl fit generic flow, it will malloc another memory address and copy whole fit image to this malloc address. But it is un-necessary for booting from RAM. This patch improves this flow by declare the board_spl_fit_buffer_addr() to replace the original one. The larger image size (eq: Kernel Image 10~20MB), it can save more booting time. Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang

riscv: ae350: Enable CCTL_SUEN

2023-02-01T08:17:34Z

CCTL operations are available to Supervisor/User-mode software under the control of the mcache_ctl.CCTL_SUEN control bit. Enable it to support Supervisor(and User) CCTL operations. Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang

riscv: Rename Andes PLIC to PLICSW

2022-11-03T05:27:56Z

As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Rick Chen

riscv: ae350: enable Coherence Manager for ae350

2021-10-07T08:08:23Z

If Coherence Manager were not set in the beginning, u-boot-spl would sometimes fail to boot to u-boot proper. Enable CM and I/D cache at the same time in harts_early_init Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen

cpu: Rename SPL_CPU_SUPPORT to SPL_CPU

2021-03-27T02:04:31Z

The _SUPPORT suffix is from an earlier time and interferes with use of the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix. Tidy up the TODO that prompted this. Signed-off-by: Simon Glass