u-boot.git/arch/riscv/cpu/cpu.c, branch master

riscv: cpu: Beautify the warning message

2025-12-08T04:10:10+00:00

Add '\n' to the end of the warning message.

Besides, if we enable console record utility,
missing the '\n' causes the console_record_readline
fail to recognize the end of string.

Signed-off-by: Leo Yu-Chi Liang

riscv: cpu: Use CONFIG_IS_ENABLED(CPU) instead of plain ifdef

2025-08-14T06:32:00+00:00

ifdef CONFIG_CPU only works in U-Boot proper but macro is not working when
XPL phases are used. In this case CONFIG_SPL_CPU is also defined and can be
disabled which is causing compilation error.

Signed-off-by: Michal Simek 
Reviewed-by: Leo Yu-Chi Liang

riscv: Access gd with inline assembly when building with LTO or Clang

2025-05-21T08:46:16+00:00

Similar to AArch64's case, Clang may wrongly fold accesses to gd pointer
which is defined with register qualifier into constants, breaking
various components.

This patch defines gd as a macro when building with Clang or LTO, which
expands to get_gd() that accesses gp pointer in assembly, making RISC-V
ports function properly and preparing for introduction of LTO in the
future. Board initialization code is also adapted for non-assignable gd.

Reported-by: Nathaniel Hourt 
Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

riscv: add a generic implementation for cleanup_before_linux()

2025-02-03T07:26:06+00:00

Most RISC-V SoCs have similar cleanup_before_linux() functions. Let's
provide a weak symbol as fallback to reduce duplicated code.

Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

riscv: Fallback to riscv,isa

2025-01-16T07:34:18+00:00

Update the cpu probing to fallback to "riscv,isa" property if
"riscv,isa-extensions" is not available and modify the riscv CMO code
to use the block size that was probed during cpu setup.

Signed-off-by: Mayuresh Chitale 
Reviewed-by: Leo Yu-Chi Liang

riscv: Enhance extension probing

2025-01-16T07:34:18+00:00

Enhance the existing extension probing mechanism by adding support for
more extensions and probing using the "riscv,isa" property. This patch
is ported from the latest upstream linux.

Signed-off-by: Mayuresh Chitale 
Reviewed-by: Leo Yu-Chi Liang

riscv: support extension probing using riscv, isa-extensions

2024-04-09T03:30:17+00:00

A new property has been added, with an extensive rationale at [1], that
can be used in place of "riscv,isa" to indicate what extensions are
supported by a given platform that is a list of strings rather than a
single string. There are some differences between the new property,
"riscv,isa-extensions" and the incumbent "riscv,isa" - chief among them
for the sake of parsing being the list of strings, as opposed to a
string. Another advantage is strictly defined meanings for each string
in a dt-binding, rather than deriving meaning from RVI standards. This
will likely to some divergence over time, but U-Boot's current use of
extension detection is very limited - there are just four callsites of
supports_extension() in mainline U-Boot.

These checks are limited to two checks for FPU support and two checks
for "s" and "u". "s" and "u" are not supported by the new property, but
they were also not permitted in "riscv,isa". These checks are only
meaningful (or run) in M-Mode, in which case supports_extension() does
not parse the devicetree anyway.

Add support for the new property in U-Boot, prioritising it, before
falling back to the, now deprecated, "riscv,isa" property if it is not
present.

Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang

riscv: don't read riscv, isa in the riscv cpu's get_desc()

2024-04-09T03:30:17+00:00

cpu_get_desc() for the RISC-V CPU currently reads "riscv,isa" to get
the description, but it is no longer a required property and cannot be
assummed to always be present, as the new "riscv,isa-extensions" and
"riscv,isa-base" properties may be present instead.

On RISC-V, cpu_get_desc() has two main uses - firstly providing an
informational name for the CPU for smbios or at boot with
DISPLAY_CPUINFO etc and secondly it forms the basis of ISA extension
detection in supports_extension() as it returns (a portion of) an ISA
string.

cpu_get_desc() returns a string, which aligned with "riscv,isa" but
the new property is a list of strings. Rather than add support for
the list of strings property, which would require creating an isa
string from "riscv,isa-extensions", modify the RISC-V CPU's
implementaion of cpu_get_desc() return the first compatible as the
cpu description instead. This may be fine for the informational cases,
but it would break extension dtection, given supports_extension()
expects cpu_get_desc() to return an ISA string.

Call dev_read_string() directly in supports_extension() to get the
contents of "riscv,isa" so that extension detection remains functional.
As a knock-on affect of this change, extension detection is no longer
broken for long ISA strings. Previously if the ISA string exceeded the
32 element array that supports_extension() passed to cpu_get_desc(),
it would return ENOSPC and no extensions would be detected.
This bug probably had no impact as U-Boot does not currently do anything
meaningful with the results of supports_extension() and most SoCs
supported by U-Boot don't have anywhere near that complex of an ISA
string. The QEMU virt machine's CPUs do however, so extension detection
doesn't work there.

Signed-off-by: Conor Dooley 
reviewed-by: Leo Yu-Chi Liang

riscv: cpu: improve multi-letter extension detection in supports_extension()

2024-03-12T06:36:13+00:00

The first multi-letter extension after the single-letter extensions does
not have to be preceded by an underscore, which could cause the parser
to mistakenly find a single-letter extension after the start of the
multi-letter portion of the string.
Three letters precede multi-letter extensions (s, x & z), none of which
are valid single-letter extensions. The dt-binding also allows
multi-letter extensions starting with h, but no such extension have been
frozen or ratified, and the unprivileged spec no longer uses "h" as a
prefix for multi-letter hypervisor extensions, having moved to "sh"
instead. For that reason, modify the parser to stop at s, x & z to prevent
this overrun, ignoring h.

Signed-off-by: Conor Dooley 
Reviewed-by: Heinrich Schuchardt

riscv: Add a reset_cpu() function

2023-12-21T21:07:52+00:00

The current do_reset() is called from a command context. Add a function
which can be used from anywhere, as is done on ARM. Adjust do_reset()
to call it.

Note that reset_cpu() is normally provided by SYSRESET so make this
declaration conditional on that being disabled.

Signed-off-by: Simon Glass 
Reviewed-by: Chanho Park 
Tested-by: Chanho Park