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<title>u-boot.git/arch/riscv/cpu/fu540/cache.c, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>board: sifive: use ccache driver instead of helper function</title>
<updated>2021-09-07T02:34:29+00:00</updated>
<author>
<name>Zong Li</name>
<email>zong.li@sifive.com</email>
</author>
<published>2021-09-01T07:01:42+00:00</published>
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<id>835210a125bef56dacb687cb9f4deae61e68e79d</id>
<content type='text'>
Invokes the common cache_init function to initialize ccache.

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
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<pre>
Invokes the common cache_init function to initialize ccache.

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
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</entry>
<entry>
<title>common: Drop asm/global_data.h from common header</title>
<updated>2021-02-02T20:33:42+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-10-31T03:38:53+00:00</published>
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Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include &lt;asm/global_data.h&gt; at all, so
remove that include.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
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<pre>
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include &lt;asm/global_data.h&gt; at all, so
remove that include.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>riscv: fu540: Use correct API to get L2 cache controller base address</title>
<updated>2020-08-25T01:33:16+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bin.meng@windriver.com</email>
</author>
<published>2020-08-18T08:09:20+00:00</published>
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<id>52dc7ae74918d01fa55ca103841a0eaa0dfa7409</id>
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At present fdtdec_get_addr() is used to get L2 cache controller base
address. This only works for a fixed #address-cells and #size-cells.
Change to use fdtdec_get_addr_size_auto_parent() instead.

Signed-off-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Pragnesh Patel &lt;pragnesh.patel@openfive.com&gt;
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<pre>
At present fdtdec_get_addr() is used to get L2 cache controller base
address. This only works for a fixed #address-cells and #size-cells.
Change to use fdtdec_get_addr_size_auto_parent() instead.

Signed-off-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Pragnesh Patel &lt;pragnesh.patel@openfive.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>riscv: sifive: fu540: redundant initialization</title>
<updated>2020-08-14T06:39:14+00:00</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2020-08-03T21:09:49+00:00</published>
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<id>6a43e3a16743e5fc5b765bf897691b630e3e1edb</id>
<content type='text'>
We should not initialize a variable if the value is overwritten before
being read.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Pragnesh Patel &lt;pragnesh.patel@sifive.com&gt;
Tested-by: Pragnesh Patel &lt;pragnesh.patel@sifive.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
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<pre>
We should not initialize a variable if the value is overwritten before
being read.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Pragnesh Patel &lt;pragnesh.patel@sifive.com&gt;
Tested-by: Pragnesh Patel &lt;pragnesh.patel@sifive.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>riscv: sifive: fu540: enable all cache ways from U-Boot proper</title>
<updated>2020-07-03T07:09:06+00:00</updated>
<author>
<name>Pragnesh Patel</name>
<email>pragnesh.patel@sifive.com</email>
</author>
<published>2020-05-29T06:44:51+00:00</published>
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<id>5ce50206ed24080707946849d3542534fadf8cbf</id>
<content type='text'>
Add L2 cache node to enable all cache ways from U-Boot proper.

Signed-off-by: Pragnesh Patel &lt;pragnesh.patel@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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<pre>
Add L2 cache node to enable all cache ways from U-Boot proper.

Signed-off-by: Pragnesh Patel &lt;pragnesh.patel@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
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</content>
</entry>
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