u-boot.git/arch/riscv/cpu/fu540, branch master

sifive: switch to OF_UPSTREAM

2026-03-12T18:56:52+00:00

Tested on HiFive Unleashed and HiFive Unmatched, both SPIFlash and MMC boot.

Signed-off-by: Andreas Schwab 
Reviewed-by: Leo Yu-Chi Liang

arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11T17:44:47+00:00

Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass

board: sifive: Rename spl_soc_init() to spl_dram_init()

2024-05-01T16:01:18+00:00

Rename spl_soc_init() to spl_dram_init() because the generic function
name does not reflect what the function actually does. Also
spl_dram_init() is commonly used for dram initialization and should be
called from board_init_f().

Signed-off-by: Lukas Funke 
Reviewed-by: Leo Yu-Chi Liang

riscv: Remove common.h usage

2023-10-24T20:34:45+00:00

We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini 
Reviewed-by: Rick Chen

common: return type board_get_usable_ram_top

2023-08-15T16:21:17+00:00

board_get_usable_ram_top() returns a physical address that is stored in
gd->ram_top. The return type of the function should be phys_addr_t like the
current type of gd->ram_top.

Signed-off-by: Heinrich Schuchardt

riscv: Rename SiFive CLINT to RISC-V ALINT

2023-07-12T05:21:40+00:00

As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.

Signed-off-by: Bin Meng 
Reviewed-by: Rick Chen

board_f: Fix types for board_get_usable_ram_top()

2022-09-23T19:12:42+00:00

Commit 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t")
changed type of ram_top member from ulong to phys_addr_t but did not
changed types in board_get_usable_ram_top() function which returns value
for ram_top.

So change ulong to phys_addr_t type also in board_get_usable_ram_top()
signature and implementations.

Fixes: 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t")
Signed-off-by: Pali Rohár 
Reviewed-by: Simon Glass

board: sifive: use ccache driver instead of helper function

2021-09-07T02:34:29+00:00

Invokes the common cache_init function to initialize ccache.

Signed-off-by: Zong Li 
Reviewed-by: Sean Anderson 
Reviewed-by: Rick Chen

drivers: clk: add fu740 support

2021-05-31T08:35:54+00:00

Add fu740 support. One abstract layer is added for supporting
multiple chips such as fu540 and fu740.

Signed-off-by: Green Wan

riscv: Split SiFive CLINT support between SPL and U-Boot proper

2021-05-17T08:42:24+00:00

At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.

This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.

To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.

Signed-off-by: Bin Meng 
Reviewed-by: Sean Anderson