u-boot.git/arch/riscv/cpu/generic, branch master

treewide: Clean up DECLARE_GLOBAL_DATA_PTR usage

2026-02-17T19:50:22+00:00

Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.

Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.

Reviewed-by: Patrice Chotard  #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal  #TI boards
Acked-by: Yao Zi  #TH1520
Signed-off-by: Peng Fan

riscv: cpu: generic: fallback to generic cleanup_before_linux()

2025-02-03T07:26:06+00:00

The current implementation is equivalent to the fallback one, so
this shouldn't change any behaviour but cleans the code up only.

Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

riscv: Remove common.h usage

2023-10-24T20:34:45+00:00

We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini 
Reviewed-by: Rick Chen

riscv: remove dram_init_banksize()

2023-10-19T09:29:32+00:00

Remove dram_init_banksize() on the architecture level.

Limiting used RAM to under 4 GiB is only necessary for CPUs which have a
DMA issue. SoC specific code already exists for FU540, FU740, JH7110.

Not all RISC-V boards will have memory below 4 GiB.

A weak implementation of dram_init_banksize() exists in common/board_f.c.

See the discussion in
https://lore.kernel.org/u-boot/545fe813-cb1e-469c-a131-0025c77aeaa2@canonical.com/T/

Signed-off-by: Heinrich Schuchardt 
Reviewed-by: Anup Patel

common: return type board_get_usable_ram_top

2023-08-15T16:21:17+00:00

board_get_usable_ram_top() returns a physical address that is stored in
gd->ram_top. The return type of the function should be phys_addr_t like the
current type of gd->ram_top.

Signed-off-by: Heinrich Schuchardt

riscv: define a cache line size for the generic CPU

2023-07-24T05:22:24+00:00

The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.

Define the cache line size for QEMU on RISC-V to be 64 bytes.

Signed-off-by: Heinrich Schuchardt 
Reviewed-by: Bin Meng

riscv: Rename SiFive CLINT to RISC-V ALINT

2023-07-12T05:21:40+00:00

As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.

Signed-off-by: Bin Meng 
Reviewed-by: Rick Chen

board_f: Fix types for board_get_usable_ram_top()

2022-09-23T19:12:42+00:00

Commit 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t")
changed type of ram_top member from ulong to phys_addr_t but did not
changed types in board_get_usable_ram_top() function which returns value
for ram_top.

So change ulong to phys_addr_t type also in board_get_usable_ram_top()
signature and implementations.

Fixes: 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t")
Signed-off-by: Pali Rohár 
Reviewed-by: Simon Glass

riscv: qemu: Switch to use binman to generate u-boot.itb

2021-05-19T09:01:51+00:00

By utilizing the newly introduced BINMAN_STANDALONE_FDT option, along
with a new dedicated device tree source file for the QEMU virt target
used for binman only, we can now use binman to generate u-boot.itb.

Signed-off-by: Bin Meng 
Reviewed-by: Simon Glass

riscv: Split SiFive CLINT support between SPL and U-Boot proper

2021-05-17T08:42:24+00:00

At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.

This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.

To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.

Signed-off-by: Bin Meng 
Reviewed-by: Sean Anderson