u-boot.git/arch/riscv/cpu/mpfs, branch master

riscv: mpfs: SIFIVE_CLINT and SPL_SIFIVE_CLINT don't exist

2026-03-12T18:57:58+00:00

Don't imply non-existent symbols CONFIG_SIFIVE_CLINT and SPL_SIFIVE_CLINT.

MPFS boards neither use SPL nor do they run main U-Boot in M-mode.
So we don't need CONFIG_(SPL_)ACLINT either.

Signed-off-by: Heinrich Schuchardt 
Acked-by: Conor Dooley

riscv: mpfs: move SoC level options to the CPU Kconfig

2025-12-08T04:10:43+00:00

There are multiple boards that use the PolarFire SoC, so extract
the Kconfig sections that are determined at a CPU level from the board
Kconfigs now that we have a CPU Kconfig.

Signed-off-by: Conor Dooley

riscv: create a custom CPU implementation for PolarFire SoC

2025-12-08T04:10:39+00:00

PolarFire SoC needs a custom implementation of top_of_ram(), so stop
using the generic CPU & create a custom CPU instead.

Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang