u-boot.git/arch/riscv/cpu/mtrap.S, branch master

riscv: Align the trap handler to 64 bytes

2023-11-02T07:15:46+00:00

This is required on CPUs which always operate in CLIC mode, such as the
T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
trap vector base address held in mtvec is constrained to be aligned on a
64-byte or larger power-of-two boundary."

Reported-by: Madushan Nishantha 
Signed-off-by: Samuel Holland 
Reviewed-by: Leo Yu-Chi Liang

riscv: Remove common.h usage

2023-10-24T20:34:45+00:00

We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini 
Reviewed-by: Rick Chen

riscv: Add option to print registers on exception

2020-02-10T06:51:08+00:00

When debugging, it can be helpful to see more information about an
unhandled exception. This patch adds an option to view the registers at
the time of the trap, similar to the linux output on a kernel panic.

Signed-off-by: Sean Anderson 
Reviewed-by: Rick Chen 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng

riscv: Return to previous privilege level after trap handling

2018-12-18T01:56:27+00:00

At present the trap handler returns to hardcoded M-mode/S-mode.
Change to returning to previous privilege level instead.

Signed-off-by: Bin Meng 
Reviewed-by: Lukas Auer 
Reviewed-by: Anup Patel

riscv: Fix context restore before returning from trap handler

2018-12-18T01:56:27+00:00

sp cannot be loaded before restoring other registers.

Signed-off-by: Bin Meng 
Reviewed-by: Lukas Auer 
Reviewed-by: Anup Patel

riscv: Move trap handler codes to mtrap.S

2018-12-18T01:56:27+00:00

Currently the M-mode trap handler codes are in start.S. For future
extension, move them to a separate file mtrap.S.

Signed-off-by: Bin Meng 
Reviewed-by: Lukas Auer 
Reviewed-by: Anup Patel