u-boot.git/arch/riscv/cpu/start.S, branch master

Revert "riscv: Add a Zalrsc-only alternative for synchronization in start.S"

2025-10-16T08:36:37+00:00

This reverts commit a681cfecb4346107212f377e2075f6eb1bdc6a2b.

It has been reported that the commit causes boot regression for SPL on
StarFive VisionFive 2 or compatible boards. Inspecting the code, I did
spot one logic error for deciding whether Zaamo or Zalrsc is used, and
it's still unclear what exactly causes the regression, let's revert it
for now.

Reported-by: E Shattow 
Link: https://lore.kernel.org/u-boot/1871663e-b918-4351-9e9e-97f9a4c73733@freeshell.de/
Signed-off-by: Yao Zi 
Acked-by: E Shattow 
Acked-by: Leo Yu-Chi Liang

riscv: Add a Zalrsc-only alternative for synchronization in start.S

2025-09-19T11:22:29+00:00

Add an alternative implementation that use Zalrsc extension only for
HART lottery and SMP locking to support SMP on cores without "Zaamo"
extension available. The Zaamo implementation is still prioritized if
both of them are available, since it takes fewer instructions.

Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

spl: Use CONFIG_VAL() to obtain the SPL stack

2025-03-13T16:36:10+00:00

Now that we have the same option for SPL and TPL, simplify the logic for
determining the initial stack.

Note that this changes behaviour as current SPL_STACK is a fallback for
TPL. However, that was likely unintended and can be handled with Kconfig
defaults if needed.

Signed-off-by: Simon Glass 
Reviewed-by: Tom Rini 
Suggested-by: Tom Rini

spl: Add an SPL_HAVE_INIT_STACK option

2025-03-13T16:36:09+00:00

At present there is a hex value SPL_STACK which both determines whether
SPL has its own initial stack and the hex value of that stack.

Split off the former into SPL_HAVE_INIT_STACK with SPL_STACK depending
on that and only providing the latter.

Signed-off-by: Simon Glass 
[trini: Resync defconfig files]

arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11T17:44:47+00:00

Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass

riscv: remove cache enablement in start.S

2024-05-30T08:01:09+00:00

Cache could be enabled in harts_early_init board-specific hook,
so remove cache enablement in start.S

Signed-off-by: Leo Yu-Chi Liang

riscv: add backtrace support

2024-04-09T03:29:38+00:00

When debugging, it is useful to have a backtrace to find
out what is in the call stack as the previous function (RA)
may not have been the culprit.

Since this adds size to the build, do not add it by default
and avoid putting it in the SPL build if not needed.

Signed-off-by: Ben Dooks 
Tested-by: Leo Yu-Chi Liang

riscv: Remove common.h usage

2023-10-24T20:34:45+00:00

We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini 
Reviewed-by: Rick Chen

riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation

2023-08-10T02:58:12+00:00

Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove
existing Starfive JH7110's L2 LIM clean code, since existing code has
following issues:
 1. Each hart (in the middle of a function call) overwriting its own
    stack and other harts' stacks.
    (data-race and data-corruption)
 2. Lottery winner hart can be doing "board_init_f_init_reserve",
    while other harts are in the middle of zeroing L2 LIM.
    (data-race)

Signed-off-by: Bo Gan 
Signed-off-by: Shengyu Qu 
Reviewed-by: Leo Yu-Chi Liang

riscv: setup per-hart stack earlier

2023-07-24T05:17:26+00:00

Harts need to use per-hart stack before any function call, even if that
function is a simple one. When the callee uses stack for register save/
restore, especially RA, if nested call, concurrent access by multiple
harts on the same stack will cause data-race.

This patch sets up SP before `board_init_f_alloc_reserve`. A side effect
of this is that the memory layout has changed as the following:

+----------------+        +----------------+ <----- SPL_STACK/
|  ......        |        |  hart 0 stack  |        SYS_INIT_SP_ADDR
|  malloc_base   |        +----------------+
+----------------+        |  hart 1 stack  |
|  GD            |        +----------------+ If not SMP, N=1
+----------------+        |  ......        |
|  hart 0 stack  |        +----------------+
+----------------+   ==>  |  hart N-1 stack|
|  hart 1 stack  |        +----------------+
+----------------+        |  ......        |
|  ......        |        |  malloc_base   |
+----------------+        +----------------+
|  hart N-1 stack|        |  GD            |
+----------------+        +----------------+
|                |        |                |

Signed-off-by: Bo Gan 
Cc: Rick Chen 
Cc: Leo 
Cc: Sean Anderson 
Cc: Bin Meng 
Cc: Lukas Auer 
Reviewed-by: Rick Chen 
Reviewed-by: Leo Yu-Chi Liang