u-boot.git/arch/riscv/cpu/th1520/cache.c, branch master Unnamed repository; edit this file 'description' to name the repository. riscv: cpu: th1520: Support cache enabling/disabling in M mode only 2025-06-09T02:44:06+00:00 Yao Zi ziyao@disroot.org 2025-05-30T09:48:48+00:00 85cfabe895f4f32a5b65c114ebef7793321d5e01 These operations rely on a customized M-mode CSR, MHCR, which isn't available when running in S mode. Let's fallback to the generic weak stub when running in S mode to avoid illegal accesses. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
These operations rely on a customized M-mode CSR, MHCR, which isn't
available when running in S mode.

Let's fallback to the generic weak stub when running in S mode to avoid
illegal accesses.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
riscv: cpu: Add TH1520 CPU support 2025-05-21T08:49:52+00:00 Yao Zi ziyao@disroot.org 2025-05-13T09:04:56+00:00 5fe9ced3552ddeb40478b56507d3b48968be2939 Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Introduce the SoC-specific code and corresponding Kconfig entries for
TH1520 SoC. Following features are implemented for TH1520,

- Cache enable/disable through customized CSR
- Invalidation of customized PMP entries
- DRAM driver probing for SPL

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>