u-boot.git/arch/riscv/cpu/th1520, branch master

treewide: Clean up DECLARE_GLOBAL_DATA_PTR usage

2026-02-17T19:50:22+00:00

Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.

Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.

Reviewed-by: Patrice Chotard  #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal  #TI boards
Acked-by: Yao Zi  #TH1520
Signed-off-by: Peng Fan

dts: th1520: Switch to upstream devicetree

2025-09-19T11:03:57+00:00

Imply OF_UPSTREAM in platform Kconfig option and adapt existing boards
to use the correct upstream devicetree paths.

Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

riscv: cpu: th1520: Limit upper RAM boundary to 4 GiB

2025-07-17T06:37:40+00:00

TH1520 SoC ships DMA peripherals that could only reach the first 32-bit
range of memory, for example, the GMAC controllers. Let's limit the
usable top of RAM below 4GiB to ensure DMA allocations are accessible to
all peripherals.

Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

riscv: cpu: th1520: Enable pinctrl by default

2025-07-03T10:10:58+00:00

Select PINCTRL_TH1520 in CPU Kconfig entry and update defconfig for
existing TH1520-based boards to ensure PINCTRL is enabled.

Signed-off-by: Yao Zi 
Acked-by: Leo Yu-Chi Liang

riscv: cpu: th1520: Add a routine to bring up secondary cores

2025-07-03T08:14:13+00:00

On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by
hardware, and the remaining HARTs are in reset states, requiring manual
setup of reset address and deassertion to function normal. Introduce a
routine to do the work.

Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init

2025-07-03T08:14:13+00:00

C910 cores integrated in TH1520 SoC provide various customized CSRs for
configuring core behavior, including cache coherency and timing, branch
predication, and clock gating for internal components.

This patch sets them up for efficient operation and satisfying
requirements of an SMP system.

Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

riscv: cpu: th1520: Support cache enabling/disabling in M mode only

2025-06-09T02:44:06+00:00

These operations rely on a customized M-mode CSR, MHCR, which isn't
available when running in S mode.

Let's fallback to the generic weak stub when running in S mode to avoid
illegal accesses.

Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

riscv: cpu: th1520: Build spl.c for SPL only

2025-06-09T02:44:06+00:00

Symbols in spl.c only function correctly in SPL stage. Build the file
for SPL only to avoid weak symbols in proper U-Boot being unexpectedly
reloaded.

Fixes: 5fe9ced3552 ("riscv: cpu: Add TH1520 CPU support")
Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

riscv: cpu: th1520: Select clock driver

2025-05-21T08:49:57+00:00

The clock driver is essential for TH1520 SoCs to operate. Select the
driver in SoC Kconfig entry.

Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

riscv: cpu: th1520: Initialize IOPMPs in SPL

2025-05-21T08:49:57+00:00

TH1520 SoC ships several IOPMPs protecting various on-chip peripherals.
They must be configured before accessing the peripherals. Let's
initialize them in SPL harts_early_init().

Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang