u-boot.git/arch/riscv/cpu, branch next

treewide: move bi_dram[] from bd to gd

2026-06-25T00:13:24Z

Currently, the bi_dram[] information is stored in the board info structure (bd). Because bd is only valid after reserve_board(), dram_init_banksize() must be called late in the initialization process. This limitation is problematic, as it forces us to rely on a variety of bespoke functions to determine board RAM, bank memory sizes, and other early setup requirements. By moving bi_dram[] into the global data (gd), we can run it earlier. This is particularly convenient since boards define their own dram_init_banksize() routines, which do not always rely on parsing Device Tree (DT) memory nodes. Additionally, U-Boot defaults to relocating to the top of the first memory bank. While boards currently use custom functions to override this behavior, having the DRAM bank information available earlier in gd makes relocating to a different bank trivial and standardizes the process. Reviewed-by: Anshul Dalal Tested-by: Michal Simek # Versal Gen 2 Vek385 Tested-by: Anshul Dalal Reviewed-by: Simon Glass Signed-off-by: Ilias Apalodimas Tested-by: Christophe Leroy (CS GROUP)

eeprom: starfive: Simplify get_ddr_size_from_eeprom()

2026-03-16T17:36:57Z

Directly return the DDR size instead of the field of 'DxxxExxx'. Move the function description to the header file. Return 0 instead of 0xFF if read_eeprom() fails. Reviewed-by: Heinrich Schuchardt Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration") Signed-off-by: Hal Feng

riscv: mpfs: SIFIVE_CLINT and SPL_SIFIVE_CLINT don't exist

2026-03-12T18:57:58Z

Don't imply non-existent symbols CONFIG_SIFIVE_CLINT and SPL_SIFIVE_CLINT. MPFS boards neither use SPL nor do they run main U-Boot in M-mode. So we don't need CONFIG_(SPL_)ACLINT either. Signed-off-by: Heinrich Schuchardt Acked-by: Conor Dooley

sifive: switch to OF_UPSTREAM

2026-03-12T18:56:52Z

Tested on HiFive Unleashed and HiFive Unmatched, both SPIFlash and MMC boot. Signed-off-by: Andreas Schwab Reviewed-by: Leo Yu-Chi Liang

treewide: Clean up DECLARE_GLOBAL_DATA_PTR usage

2026-02-17T19:50:22Z

Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and drop the unnecessary inclusion of asm/global_data.h. Headers should be included directly by the files that need them, rather than indirectly via global_data.h. Reviewed-by: Patrice Chotard #STMicroelectronics boards and STM32MP1 ram test driver Tested-by: Anshul Dalal #TI boards Acked-by: Yao Zi #TH1520 Signed-off-by: Peng Fan

riscv: Update linker scripts to ensure appended device tree is aligned

2026-01-20T18:07:21Z

With commit 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our device tree is not 8-byte aligned. In commit 85f586035d75 ("ARM: OMAP2+: Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains that we must have ALIGN(x) statements inside of a section to ensure that padding is included and not simply that the linker address counter is incremented. To that end, this patch: - Aligns the final section before _end (for U-Boot) or _image_binary_end (for xPL phases) by 8-bytes by adding '. = ALIGN(8);' to the final section before the symbol. - Remove a now-spurious '. = ALIGN(x);' statement that was intended to provide the above alignments. - Ensure that we do have alignment by adding an ASSERT so that when not aligned we fail to link (and explain why). Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Ilias Apalodimas Signed-off-by: Tom Rini

riscv: mpfs: move SoC level options to the CPU Kconfig

2025-12-08T04:10:43Z

There are multiple boards that use the PolarFire SoC, so extract the Kconfig sections that are determined at a CPU level from the board Kconfigs now that we have a CPU Kconfig. Signed-off-by: Conor Dooley

riscv: create a custom CPU implementation for PolarFire SoC

2025-12-08T04:10:39Z

PolarFire SoC needs a custom implementation of top_of_ram(), so stop using the generic CPU & create a custom CPU instead. Signed-off-by: Conor Dooley Reviewed-by: Leo Yu-Chi Liang

riscv: cpu: Beautify the warning message

2025-12-08T04:10:10Z

Add '\n' to the end of the warning message. Besides, if we enable console record utility, missing the '\n' causes the console_record_readline fail to recognize the end of string. Signed-off-by: Leo Yu-Chi Liang

Revert "riscv: Add a Zalrsc-only alternative for synchronization in start.S"

2025-10-16T08:36:37Z

This reverts commit a681cfecb4346107212f377e2075f6eb1bdc6a2b. It has been reported that the commit causes boot regression for SPL on StarFive VisionFive 2 or compatible boards. Inspecting the code, I did spot one logic error for deciding whether Zaamo or Zalrsc is used, and it's still unclear what exactly causes the regression, let's revert it for now. Reported-by: E Shattow Link: https://lore.kernel.org/u-boot/1871663e-b918-4351-9e9e-97f9a4c73733@freeshell.de/ Signed-off-by: Yao Zi Acked-by: E Shattow Acked-by: Leo Yu-Chi Liang