u-boot.git/arch/riscv/cpu, branch v2018.03Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/arch/riscv/cpu?h=v2018.032018-01-12T13:05:12Zriscv: cpu: Add nx25 to support RISC-V2018-01-12T13:05:12ZRick Chenrick@andestech.com2017-12-26T05:55:48Zurn:sha1:e8e39597a33cc53aacbaf4ef5cae60ed86d6a20a
Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch
Verifications:
1. startup and relocation ok.
2. boot from rom or ram both ok.
2. timer driver ok.
3. uart driver ok
4. mmc driver ok
5. spi driver ok.
6. 32/64 bit both ok.
Detail verification message please see doc/README.ae250.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>