u-boot.git/arch/riscv/cpu, branch v2020.01

riscv: add option to wait for ack from secondary harts in smp functions

2019-12-10T00:23:10Z

Add a wait option to smp_call_function() to wait for the secondary harts to acknowledge the call-function request. The request is considered to be acknowledged once each secondary hart has cleared the corresponding IPI. As part of the call-function request, the secondary harts invalidate the instruction cache after clearing the IPI. This adds a delay between acknowledgment (clear IPI) and fulfillment (call function) of the request. We want to use the acknowledgment to be able to judge when the request has been completed. Remove the delay by clearing the IPI after cache invalidation and just before calling the function from the request. Signed-off-by: Lukas Auer Reviewed-by: Rick Chen Tested-by: Rick Chen Reviewed-by: Anup Patel

riscv: Fix clear bss loop in the start-up code

2019-12-10T00:23:10Z

For RV64, it will use sd instruction to clear t0 register, and the increament will be 8 bytes. So if the difference between__bss_strat and __bss_end was not 8 bytes aligned, the clear bss loop will overflow and acks like system hang. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao

riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

2019-12-10T00:23:10Z

The mcache_ctl csr only can be manipulated in M mode. Add SPL_RISCV_MMODE for U-Boot SPL to control cache operation. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao

riscv: ax25: add SPL support

2019-12-10T00:23:10Z

The U-Boot SPL will boot in M mode and load the FIT image which include OpenSBI and U-Boot proper images. After loading progress, it will jump to OpenSBI first and then U-Boot proper which will run in S mode. Also remove V5L2_CACHE due to U-Boot SPL code size consideration. Without this concern, it can be enable manually for performance. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao

common: Move board_get_usable_ram_top() out of common.h

2019-12-02T23:25:04Z

Move this function into init.h which seems to be designed for this sort of thing. Also update the header to declare struct global_data so that it can be included without global_data.h being needed. Signed-off-by: Simon Glass Reviewed-by: Tom Rini

common: Move enable/disable_interrupts out of common.h

2019-12-02T23:25:01Z

Move these two functions into the irq_funcs.h header file. Also move interrupt_handler_t as this is used by the irq_install_handler() function. Signed-off-by: Simon Glass Reviewed-by: Tom Rini

common: Move ARM cache operations out of common.h

2019-12-02T23:24:58Z

These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass Reviewed-by: Daniel Schwierzeck Reviewed-by: Tom Rini

common: Move some cache and MMU functions out of common.h

2019-12-02T23:23:55Z

These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass Reviewed-by: Tom Rini

riscv: cache: use CCTL to flush d-cache

2019-09-03T01:31:03Z

Use CCTL command to do d-cache write back and invalidate instead of fence. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng

riscv: cache: Flush L2 cache before jump to linux

2019-09-03T01:31:03Z

Flush and disable L2 cache in dcache_disable() which will be called in cleanup_before_linux() before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng