u-boot.git/arch/riscv/include/asm/arch-andes, branch master

andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND

2024-05-30T08:01:13Z

Use CSR_UCCTLCOMMAND instead of CSR_MCCTLCOMMAND to do cache flush operation in M-mode and S-mode. Signed-off-by: Leo Yu-Chi Liang

andes: cpu: Enable cache and TLB ECC support

2023-12-27T09:29:07Z

Andes CPU supports cache and TLB ECC. Enable them by default. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin

andes: cpu: Enable memboost feature

2023-12-27T09:29:07Z

Andes CPU has memboost feature including prefetch, write-around and non-blocking load. Enable them by default. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin

andes: csr.h: Clean up CSR definition

2023-12-27T09:29:07Z

Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin

riscv: Remove common.h usage

2023-10-24T20:34:45Z

We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini Reviewed-by: Rick Chen

riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()

2023-02-17T11:07:48Z

As the OpenSBI v1.2 does not enable the cache [0], we enable the i/d-cache in harts_early_init() and do not disable in cleanup_before_linux(). This patch also simplifies the logic and moves the CSR encoding to include/asm/arch-andes/csr.h. [0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen