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<title>u-boot.git/arch/riscv/include/asm/arch-generic, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>dm: treewide: Rename ..._platdata variables to just ..._plat</title>
<updated>2020-12-13T23:51:09+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-12-03T23:55:23+00:00</published>
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<id>8a8d24bdf174851ebb8607f359d54b72e3283b97</id>
<content type='text'>
Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>gpio: sifive: add support for DM based gpio driver for FU540-SoC</title>
<updated>2019-10-18T01:04:01+00:00</updated>
<author>
<name>Sagar Shrikant Kadam</name>
<email>sagar.kadam@sifive.com</email>
</author>
<published>2019-10-01T17:00:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d26b40450ba70dfc1c018c9dfc0b9b18c0465d9e'/>
<id>d26b40450ba70dfc1c018c9dfc0b9b18c0465d9e</id>
<content type='text'>
This patch adds a DM based driver model for gpio controller present in
FU540-C000 SoC on HiFive Unleashed A00 board. This SoC has one GPIO
bank and 16 GPIO lines in total, out of which GPIO0 to GPIO9 and
GPIO15 are routed to the J1 header on the board.

This implementation is ported from linux based gpio driver submitted
for review by Wesley W. Terpstra &lt;wesley@sifive.com&gt; and/or Atish Patra
&lt;atish.patra@wdc.com&gt; (many thanks !!). The linux driver can be referred
here [1]

[1]: https://lkml.org/lkml/2018/10/9/1103

Signed-off-by: Sagar Shrikant Kadam &lt;sagar.kadam@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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<pre>
This patch adds a DM based driver model for gpio controller present in
FU540-C000 SoC on HiFive Unleashed A00 board. This SoC has one GPIO
bank and 16 GPIO lines in total, out of which GPIO0 to GPIO9 and
GPIO15 are routed to the J1 header on the board.

This implementation is ported from linux based gpio driver submitted
for review by Wesley W. Terpstra &lt;wesley@sifive.com&gt; and/or Atish Patra
&lt;atish.patra@wdc.com&gt; (many thanks !!). The linux driver can be referred
here [1]

[1]: https://lkml.org/lkml/2018/10/9/1103

Signed-off-by: Sagar Shrikant Kadam &lt;sagar.kadam@sifive.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>riscv: Add place-holder asm/arch/clk.h for driver compilation</title>
<updated>2019-02-27T01:12:33+00:00</updated>
<author>
<name>Anup Patel</name>
<email>Anup.Patel@wdc.com</email>
</author>
<published>2019-02-25T08:14:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1fa625b8e4b299560e3d3f705e0ea9efc01187ad'/>
<id>1fa625b8e4b299560e3d3f705e0ea9efc01187ad</id>
<content type='text'>
Some of the drivers (such as Cadence MACB ethernet driver) expect
asm/arch/clk.h to be provided by arch support so we add place-holder
asm/arch-generic/clk.h for RISC-V generic CPU.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
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<pre>
Some of the drivers (such as Cadence MACB ethernet driver) expect
asm/arch/clk.h to be provided by arch support so we add place-holder
asm/arch-generic/clk.h for RISC-V generic CPU.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</pre>
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</content>
</entry>
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