u-boot.git/arch/riscv/include/asm/arch-th1520, branch master

riscv: cpu: th1520: Add a routine to bring up secondary cores

2025-07-03T08:14:13Z

On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by hardware, and the remaining HARTs are in reset states, requiring manual setup of reset address and deassertion to function normal. Introduce a routine to do the work. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang

riscv: cpu: th1520: Initialize IOPMPs in SPL

2025-05-21T08:49:57Z

TH1520 SoC ships several IOPMPs protecting various on-chip peripherals. They must be configured before accessing the peripherals. Let's initialize them in SPL harts_early_init(). Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang

riscv: cpu: Add TH1520 CPU support

2025-05-21T08:49:52Z

Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang