u-boot.git/arch/riscv/include/asm/global_data.h, branch master

riscv: remove volatile from set_gd prototype

2025-06-13T22:57:15+00:00

It's slightly ironic that riscv at very first had the gd pointer
volatile qualified [6020faf62c3 ("riscv: nx25: include: Add header
files to support RISC-V")], removed that back in 2018
[40717eb849c ("riscv: checkpatch: Fix use of volatile")], and then in
2020 this helper was added [6b9966e1aa3 ("riscv: define function
set_gd()")] which needlessly had volatile in the prototype.

Signed-off-by: Rasmus Villemoes

riscv: Access gd with inline assembly when building with LTO or Clang

2025-05-21T08:46:16+00:00

Similar to AArch64's case, Clang may wrongly fold accesses to gd pointer
which is defined with register qualifier into constants, breaking
various components.

This patch defines gd as a macro when building with Clang or LTO, which
expands to get_gd() that accesses gp pointer in assembly, making RISC-V
ports function properly and preparing for introduction of LTO in the
future. Board initialization code is also adapted for non-assignable gd.

Reported-by: Nathaniel Hourt 
Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

riscv: resume needs to be a global

2024-10-29T11:58:14+00:00

If we take an exception before u-boot is relocated, there's a good
chance we will end up in an endless loop of exceptions because resume is
invalid until after relocation.

Signed-off-by: Anton Blanchard 
Reviewed-by: Leo Yu-Chi Liang

riscv: add ACPI fields to global data

2024-01-07T20:49:15+00:00

Add fields for the location of ACPI tables to the global data.

Signed-off-by: Heinrich Schuchardt 
Reviewed-by: Simon Glass 
Reviewed-by: Bin Meng

global: Rework architecture global_data.h to include

2023-12-21T13:54:37+00:00

In most cases, the architecture global data currently makes use of
assorted linux types, but does not include  to provide
them. Add  instead of relying on indirect inclusion.

Reviewed-by: Simon Glass 
Signed-off-by: Tom Rini

Record the position of the SMBIOS tables

2023-09-21T22:05:40+00:00

Remember where these end up so that we can pass this information on to
the EFI layer.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng

riscv: Rename SiFive CLINT to RISC-V ALINT

2023-07-12T05:21:40+00:00

As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.

Signed-off-by: Bin Meng 
Reviewed-by: Rick Chen

riscv: global_data.h: Correct the comment for PLICSW

2023-02-17T11:07:48+00:00

PLIC is used for external interrupt, while PLICSW is an Andes-specific
design for software interrupt.

Signed-off-by: Yu Chien Peter Lin 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Rick Chen

riscv: Rename Andes PLIC to PLICSW

2022-11-03T05:27:56+00:00

As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.

Signed-off-by: Yu Chien Peter Lin 
Reviewed-by: Rick Chen

riscv: Introduce AVAILABLE_HARTS

2022-09-26T06:29:13+00:00

In SMP all harts will register themself in available_hart
during start up. Then main hart will send IPI to other harts
according to this variables. But this mechanism may not
guarantee that all other harts can jump to next stage.

When main hart is sending IPI to other hart according to
available_harts, but other harts maybe still not finish the
registration. Then the SMP booting will miss some harts finally.
So let it become an option and it will be enabled by default.

Please refer to the discussion:
https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html

Signed-off-by: Rick Chen 
Reviewed-by: Leo Yu-Chi Liang