u-boot.git/arch/riscv/include/asm/string.h, branch master Unnamed repository; edit this file 'description' to name the repository. riscv: Add Zbb support for building U-Boot 2023-10-19T09:29:50+00:00 Yu Chien Peter Lin peterlin@andestech.com 2023-08-09T10:49:30+00:00 bc5a50452bd42029d6587e1596b44ff235655e90 This patch adds ISA string to the -march to generate zbb instructions for U-Boot binaries, along with optimized string functions introduced from Linux kernel. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
This patch adds ISA string to the -march to generate zbb instructions
for U-Boot binaries, along with optimized string functions introduced
from Linux kernel.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
riscv: assembler versions of memcpy, memmove, memset 2021-04-08T07:37:29+00:00 Heinrich Schuchardt xypron.glpk@gmx.de 2021-03-27T11:37:04+00:00 8f0dc4cfd106edbb8f8efb4583b33ecd52610e6c Provide optimized versions of memcpy(), memmove(), memset() copied from the Linux kernel. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Provide optimized versions of memcpy(), memmove(), memset() copied from
the Linux kernel.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
riscv: checkpatch: Fix Macro argument reuse 2018-03-30T05:13:22+00:00 Rick Chen rick@andestech.com 2018-02-12T03:07:58+00:00 bc0818a6a94429f2abd070afaa489266e78bf86b It is CHECK reported by checkpatch.pl CHECK: Macro argument reuse 'PTE' - possible side-effects? Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> 
It is CHECK reported by checkpatch.pl
CHECK: Macro argument reuse 'PTE' - possible side-effects?

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
riscv: nx25: include: Add header files to support RISC-V 2018-01-12T13:05:12+00:00 Rick Chen rick@andestech.com 2017-12-26T05:55:51+00:00 6020faf62c3bfb8677378d6c31e50f103bc06114 Add header files for RISC-V. Cache, ptregs, data type and other definitions are included. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> 
Add header files for RISC-V.
Cache, ptregs, data type and other definitions are included.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>