u-boot.git/arch/riscv/include/asm/syscon.h, branch master

riscv: Rename SiFive CLINT to RISC-V ALINT

2023-07-12T05:21:40+00:00

As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.

Signed-off-by: Bin Meng 
Reviewed-by: Rick Chen

riscv: Rename Andes PLIC to PLICSW

2022-11-03T05:27:56+00:00

As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.

Signed-off-by: Yu Chien Peter Lin 
Reviewed-by: Rick Chen

riscv: Rework Andes PLMT as a UCLASS_TIMER driver

2020-09-30T00:54:45+00:00

This converts the PLMT driver from the riscv-specific timer interface to be
a DM-based UCLASS_TIMER driver.

The clock-frequency/clocks properties are preferred over timebase-frequency
for two reasons. First, properties which affect a device should be located
near its binding in the device tree. Using timebase-frequency only really
makes sense when the cpu itself is the timer device. This is the case when
we read the time from a CSR, but not when there is a separate device.
Second, it lets the device use the clock subsystem which adds flexibility.
If the device is configured for a different clock speed, the timer can
adjust itself.

Signed-off-by: Sean Anderson 
Reviewed-by: Rick Chen

riscv: Add a SYSCON driver for Andestech's PLMT

2019-04-08T01:45:08+00:00

The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer

riscv: Add a SYSCON driver for Andestech's PLIC

2019-04-08T01:45:08+00:00

The Platform-Level Interrupt Controller (PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt. It is required
for handling IPI.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer

riscv: Add a SYSCON driver for SiFive's Core Local Interruptor

2018-12-18T01:56:26+00:00

This adds U-Boot syscon driver for SiFive's Core Local Interruptor
(CLINT). The CLINT block holds memory-mapped control and status
registers associated with software and timer interrupts.

This driver implements the riscv_get_time() API as required by
the generic RISC-V timer driver, as well as some other APIs that
are needed for handling IPI.

Signed-off-by: Bin Meng 
Reviewed-by: Lukas Auer 
Reviewed-by: Anup Patel