u-boot.git/arch/riscv/include/asm, branch next Unnamed repository; edit this file 'description' to name the repository. Merge patch series "bootm: Clean up arch-specific, pre-OS clean-up" 2026-03-19T00:36:50+00:00 Tom Rini trini@konsulko.com 2026-03-19T00:36:50+00:00 eb00c710508d09b2a3b9aca75dd18280f1304703 Simon Glass <sjg@chromium.org> says: Each arch does something slightly different before booting the OS. Some archs even do different things depending on the CPU type. It is quite hard to know what actually happens in the final milliseconds before the OS boot. This series attempts to start cleaning up U-Boot in this area. The basic intent is to create a new bootm_final() function which can be called by all archs. It provides some flags for a couple of necessary variations but otherwise it is generic. All architectures are converted over to use this new function. board_quiesce_devices() is moved into bootm_final() so that all archs benefit from it. This series fixes a bug in device_remove() is fixed where removing a parent with specialised flags (e.g. DM_REMOVE_ACTIVE_ALL) could leave children activated, since they do not match the flags. This fixes is needed to avoid bootm_final() causing test failures on sandbox. Future work could take this a little further: - Convert EFI loader to use the same function - Improve comments for cleanup_before_linux() across architectures - Support fake-run tracing on all archs Link: https://lore.kernel.org/r/20260306023638.2678886-1-sjg@chromium.org 
Simon Glass <sjg@chromium.org> says:

Each arch does something slightly different before booting the OS. Some
archs even do different things depending on the CPU type.

It is quite hard to know what actually happens in the final milliseconds
before the OS boot.

This series attempts to start cleaning up U-Boot in this area.

The basic intent is to create a new bootm_final() function which can be
called by all archs. It provides some flags for a couple of necessary
variations but otherwise it is generic.

All architectures are converted over to use this new function.

board_quiesce_devices() is moved into bootm_final() so that all archs
benefit from it.

This series fixes a bug in device_remove() is fixed where removing a
parent with specialised flags (e.g. DM_REMOVE_ACTIVE_ALL) could leave
children activated, since they do not match the flags. This fixes is
needed to avoid bootm_final() causing test failures on sandbox.

Future work could take this a little further:
- Convert EFI loader to use the same function
- Improve comments for cleanup_before_linux() across architectures
- Support fake-run tracing on all archs

Link: https://lore.kernel.org/r/20260306023638.2678886-1-sjg@chromium.org
riscv: Call bootm_final() 2026-03-18T19:17:34+00:00 Simon Glass simon.glass@canonical.com 2026-03-06T02:36:15+00:00 aa5ada5447369849c82310073270ed64df1efd9b The RISC-V announce_and_cleanup() duplicates the common pre-boot steps. Replace it with a call to bootm_final(). Move board_quiesce_devices() into bootm_final() so it is available to all architectures. Drop the RISC-V weak definition and header declaration since the generic one in bootm.h is used instead. Signed-off-by: Simon Glass <simon.glass@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com> 
The RISC-V announce_and_cleanup() duplicates the common pre-boot
steps. Replace it with a call to bootm_final().

Move board_quiesce_devices() into bootm_final() so it is available to
all architectures. Drop the RISC-V weak definition and header
declaration since the generic one in bootm.h is used instead.

Signed-off-by: Simon Glass <simon.glass@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
eeprom: starfive: Correct get_pcb_revision_from_eeprom() 2026-03-16T17:36:57+00:00 Hal Feng hal.feng@starfivetech.com 2025-10-24T08:59:27+00:00 78253aeeecdfea4c71779905ff2b400fa7400b1c pcb_revision is stored in the pcb_revision field of ATOM4. Correct it. Move the function description to the header file. Return 0 instead of 0xFF if read_eeprom() fails. Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration") Signed-off-by: Hal Feng <hal.feng@starfivetech.com> 
pcb_revision is stored in the pcb_revision field of ATOM4. Correct it.
Move the function description to the header file.
Return 0 instead of 0xFF if read_eeprom() fails.

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
eeprom: starfive: Simplify get_ddr_size_from_eeprom() 2026-03-16T17:36:57+00:00 Hal Feng hal.feng@starfivetech.com 2025-10-24T08:59:26+00:00 6015c98be50f2fc571c294d2f2b0768212fb7e99 Directly return the DDR size instead of the field of 'DxxxExxx'. Move the function description to the header file. Return 0 instead of 0xFF if read_eeprom() fails. Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration") Signed-off-by: Hal Feng <hal.feng@starfivetech.com> 
Directly return the DDR size instead of the field of 'DxxxExxx'.
Move the function description to the header file.
Return 0 instead of 0xFF if read_eeprom() fails.

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
riscv: create a custom CPU implementation for PolarFire SoC 2025-12-08T04:10:39+00:00 Conor Dooley conor.dooley@microchip.com 2025-11-19T12:38:42+00:00 4d056a2037d3b4604ce2592d40ae24c6d7cf03bf PolarFire SoC needs a custom implementation of top_of_ram(), so stop using the generic CPU & create a custom CPU instead. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
PolarFire SoC needs a custom implementation of top_of_ram(), so stop
using the generic CPU & create a custom CPU instead.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv: Remove unused macro in encoding.h 2025-09-19T11:23:17+00:00 Greentime Hu greentime.hu@sifive.com 2025-09-15T07:44:27+00:00 36d9587fa8b3590ae07ca16a2fe2aa6c905fc102 This patch remove the unused macro DRAM_BASE. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
This patch remove the unused macro DRAM_BASE.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
riscv: byteorder: add test for big-endian 2025-07-03T10:10:50+00:00 Ben Dooks ben.dooks@codethink.co.uk 2025-06-13T16:12:58+00:00 364627596c7142d837912acea0d785ecdfeab676 Test for big-endian either via __RISCVEB__ which migth be rather old, or check the BYTE_ORDER if the compiler defines it (which should be any modern gcc like v12) Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Test for big-endian either via __RISCVEB__ which migth be
rather old, or check the BYTE_ORDER if the compiler defines
it (which should be any modern gcc like v12)

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
riscv: cpu: th1520: Add a routine to bring up secondary cores 2025-07-03T08:14:13+00:00 Yao Zi ziyao@disroot.org 2025-06-06T04:28:02+00:00 f28911368eaf1b403e85ac0346fadee3fa21b6c4 On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by hardware, and the remaining HARTs are in reset states, requiring manual setup of reset address and deassertion to function normal. Introduce a routine to do the work. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by
hardware, and the remaining HARTs are in reset states, requiring manual
setup of reset address and deassertion to function normal. Introduce a
routine to do the work.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
riscv: remove volatile from set_gd prototype 2025-06-13T22:57:15+00:00 Rasmus Villemoes ravi@prevas.dk 2025-06-04T19:56:12+00:00 ae86cd8c59fe08c9a37d14dbd6e42190dda2a0d4 It's slightly ironic that riscv at very first had the gd pointer volatile qualified [6020faf62c3 ("riscv: nx25: include: Add header files to support RISC-V")], removed that back in 2018 [40717eb849c ("riscv: checkpatch: Fix use of volatile")], and then in 2020 this helper was added [6b9966e1aa3 ("riscv: define function set_gd()")] which needlessly had volatile in the prototype. Signed-off-by: Rasmus Villemoes <ravi@prevas.dk> 
It's slightly ironic that riscv at very first had the gd pointer
volatile qualified [6020faf62c3 ("riscv: nx25: include: Add header
files to support RISC-V")], removed that back in 2018
[40717eb849c ("riscv: checkpatch: Fix use of volatile")], and then in
2020 this helper was added [6b9966e1aa3 ("riscv: define function
set_gd()")] which needlessly had volatile in the prototype.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Revert "riscv: Select appropriate image type" 2025-06-02T08:17:55+00:00 Mayuresh Chitale mchitale@ventanamicro.com 2025-05-29T03:30:50+00:00 29a2025d77192e510580403b793ae027af19c81c This reverts commit 027a316828528da95a77d20632370b1bc2823f0b as discussed in [1]. [1] https://lists.denx.de/pipermail/u-boot/2025-May/590841.html Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
This reverts commit 027a316828528da95a77d20632370b1bc2823f0b as
discussed in [1].

[1] https://lists.denx.de/pipermail/u-boot/2025-May/590841.html

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>