u-boot.git/arch/riscv/include, branch v2020.01

riscv: add option to wait for ack from secondary harts in smp functions

2019-12-10T00:23:10Z

Add a wait option to smp_call_function() to wait for the secondary harts to acknowledge the call-function request. The request is considered to be acknowledged once each secondary hart has cleared the corresponding IPI. As part of the call-function request, the secondary harts invalidate the instruction cache after clearing the IPI. This adds a delay between acknowledgment (clear IPI) and fulfillment (call function) of the request. We want to use the acknowledgment to be able to judge when the request has been completed. Remove the delay by clearing the IPI after cache invalidation and just before calling the function from the request. Signed-off-by: Lukas Auer Reviewed-by: Rick Chen Tested-by: Rick Chen Reviewed-by: Anup Patel

gpio: sifive: add support for DM based gpio driver for FU540-SoC

2019-10-18T01:04:01Z

This patch adds a DM based driver model for gpio controller present in FU540-C000 SoC on HiFive Unleashed A00 board. This SoC has one GPIO bank and 16 GPIO lines in total, out of which GPIO0 to GPIO9 and GPIO15 are routed to the J1 header on the board. This implementation is ported from linux based gpio driver submitted for review by Wesley W. Terpstra and/or Atish Patra (many thanks !!). The linux driver can be referred here [1] [1]: https://lkml.org/lkml/2018/10/9/1103 Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Bin Meng

riscv: add SPL support

2019-08-26T08:07:42Z

U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly jumping to the image and via OpenSBI firmware. In the first case, both U-Boot SPL and proper must be compiled to run in the same privilege mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine mode and U-Boot proper for supervisor mode. To be able to use SPL, boards have to provide a supported SPL boot device. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel

riscv: add run mode configuration for SPL

2019-08-26T08:07:42Z

U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel

riscv: Access CSRs using CSR numbers

2019-08-15T05:42:28Z

We should prefer accessing CSRs using their CSR numbers because: 1. It compiles fine with older toolchains. 2. We can use latest CSR names in #define macro names of CSR numbers as-per RISC-V spec. 3. We can access newly added CSRs even if toolchain does not recognize newly added CSRs by name. This commit is inspired from Linux kernel commit a3182c91ef4e ("RISC-V: Access CSRs using CSR numbers"). Signed-off-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Anup Patel Reviewed-by: Lukas Auer

riscv: Sync csr.h with Linux kernel v5.2

2019-08-15T05:42:28Z

This syncs csr.h with Linux kernel 5.2, and imports asm.h that is required by csr.h. Signed-off-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Anup Patel Reviewed-by: Lukas Auer

env: Drop environment.h header file where not needed

2019-08-11T20:43:41Z

This header file is now only used by files that access internal environment features. Drop it from various places where it is not needed. Acked-by: Joe Hershberger Signed-off-by: Simon Glass

riscv: Introduce CONFIG_XIP to support booting from flash

2019-05-09T08:46:46Z

When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Lukas Auer Reviewed-by: Bin Meng

riscv: Add a SYSCON driver for Andestech's PLMT

2019-04-08T01:45:08Z

The platform-Level Machine Timer (PLMT) block holds memory-mapped mtime register associated with timer tick. This driver implements the riscv_get_time() which is required by the generic RISC-V timer driver. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer

riscv: Add a SYSCON driver for Andestech's PLIC

2019-04-08T01:45:08Z

The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer