u-boot.git/arch/riscv/lib/cache.c, branch next

treewide: Add a function to change page permissions

2025-03-14T11:37:54+00:00

For armv8 we are adding proper page permissions for the relocated U-Boot
binary. Add a weak function that can be used across architectures to change
the page permissions

Tested-by: Neil Armstrong  # on AML-S905X-CC
Signed-off-by: Ilias Apalodimas

riscv: Fallback to riscv,isa

2025-01-16T07:34:18+00:00

Update the cpu probing to fallback to "riscv,isa" property if
"riscv,isa-extensions" is not available and modify the riscv CMO code
to use the block size that was probed during cpu setup.

Signed-off-by: Mayuresh Chitale 
Reviewed-by: Leo Yu-Chi Liang

riscv: cache: Add CBO instructions

2024-10-28T10:56:54+00:00

Define CBO inval and flush instructions and use those for the
dcache inval and flush operations respectively.

Signed-off-by: Mayuresh Chitale 
Reviewed-by: Leo Yu-Chi Liang

riscv: Weakly define invalidate_icache_range()

2023-11-02T07:15:54+00:00

Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
vendor-specific way to invalidate a portion of the instruction cache.
Allow them to override invalidate_icache_range().

Signed-off-by: Samuel Holland 
Reviewed-by: Leo Yu-Chi Liang

riscv: Remove common.h usage

2023-10-24T20:34:45+00:00

We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini 
Reviewed-by: Rick Chen

common: board_r: support enable_caches for RISC-V

2021-09-07T02:34:29+00:00

The enable_caches is a generic hook for architecture-implemented, we
leverage this function to enable caches for RISC-V

Signed-off-by: Zong Li 
Reviewed-by: Rick Chen

common: Move some cache and MMU functions out of common.h

2019-12-02T23:23:55+00:00

These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.

Move them over.

Signed-off-by: Simon Glass 
Reviewed-by: Tom Rini

riscv: use invalidate/flush_*cache_range functions in cache.c

2019-01-15T01:36:31+00:00

The flush_cache() function in lib/cache.c ignores its arguments and
flushes the complete data and instruction caches. Use the
invalidate/flush_*cache_range() functions instead to only flush the
requested memory region.

This patch does not change the current behavior of U-Boot, since the
implementation of the invalidate/flush_*cache_range() functions flush
the complete data and instruction caches. It is in preparation for CPUs
with the necessary functionality for flushing a selectable memory range.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng

riscv: move the AX25-specific implementation of flush_dcache_all

2019-01-15T01:36:31+00:00

The fence instruction is used to enforce device I/O and memory ordering
constraints in RISC-V. It can not be relied on to directly affect the
data cache on every CPU.
Andes' AX25 does not have a coherence agent. Its fence instruction
flushes the data cache and is used to keep data in the system coherent.
The implementation of flush_dcache_all in lib/cache.c is therefore
specific to the AX25. Move it into the AX25-specific cache.c in
cpu/ax25/.

This also adds a missing new line between flush_dcache_all and
flush_dcache_range in lib/cache.c.

Signed-off-by: Lukas Auer 
Reviewed-by: Bin Meng

riscv: cache: Implement i/dcache [status, enable, disable]

2018-11-26T05:58:01+00:00

AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.

This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.

This approach also provide the expansion when the
vender specific features are going to join in.

Signed-off-by: Rick Chen 
Cc: Greentime Hu