u-boot.git/arch/riscv/lib/interrupts.c, branch master

riscv: resume needs to be a global

2024-10-29T11:58:14+00:00

If we take an exception before u-boot is relocated, there's a good
chance we will end up in an endless loop of exceptions because resume is
invalid until after relocation.

Signed-off-by: Anton Blanchard 
Reviewed-by: Leo Yu-Chi Liang

riscv: allow to enable SHOW_REGS in main U-Boot only

2024-09-10T02:10:43+00:00

To minimize SPL size it is reasonable to disable SHOW_REGS. For main U-Boot
the size restrictions are much more relaxed.

* Provide separate Kconfig symbols for SPL and main U-Boot.
* Add a help text.

Signed-off-by: Heinrich Schuchardt 
Reviewed-by: Leo Yu-Chi Liang

riscv: simplify backtrace report

2024-05-14T10:40:22+00:00

* We already have a header 'backtrace', there is no need to repeat the
  word backtrace on every line.
* Add a blank line before the backtrace section of the crash report for
  improved readability.
* If U-Boot is compiled without backtrace, there is no need to write a
  message at all.
* Avoid #ifdef. We prefer functions to always be compiled and let
  the linker remove them if not needed.
* Foresee 3 digits for the backtrace index.

For testing the 'exception' command can be used.

Signed-off-by: Heinrich Schuchardt 
Reviewed-by: Leo Yu-Chi Liang

riscv: add backtrace support

2024-04-09T03:29:38+00:00

When debugging, it is useful to have a backtrace to find
out what is in the call stack as the previous function (RA)
may not have been the culprit.

Since this adds size to the build, do not add it by default
and avoid putting it in the SPL build if not needed.

Signed-off-by: Ben Dooks 
Tested-by: Leo Yu-Chi Liang

riscv: allow resume after exception

2023-11-02T08:22:06+00:00

If CSRs like seed are readable by S-mode, may not be determinable by
S-mode. For safe driver probing allow to resume via a longjmp after an
exception.

Signed-off-by: Heinrich Schuchardt 
Reviewed-by: Leo Yu-Chi Liang

riscv: Remove common.h usage

2023-10-24T20:34:45+00:00

We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini 
Reviewed-by: Rick Chen

arch/riscv: add semihosting support for RISC-V

2022-12-08T07:15:58+00:00

We add RISC-V semihosting based serial console for JTAG based early
debugging.

The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc

Signed-off-by: Anup Patel 
Signed-off-by: Kautuk Consul 
Reviewed-by: Leo Yu-Chi Liang

riscv: show code leading to exception

2021-09-07T02:34:29+00:00

To make analyzing exceptions easier output the code that leads to it.
We already do the same on the ARM platform.

Here is an example:

    => exception ebreak
    Unhandled exception: Breakpoint
    EPC: 000000008ff5d50e RA: 000000008ff5d62c TVAL: 0000000000000000
    EPC: 000000008020b50e RA: 000000008020b62c reloc adjusted

    Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)

To disassemble the code we can use the decodecode script:

    $ echo 'Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)' | \
      CROSS_COMPILE=riscv64-linux-gnu- scripts/decodecode

    Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)
    All code
    ========
       0:   2785                    addiw   a5,a5,1
       2:   07a00693                li      a3,122
       6:   fef6dce3                bge     a3,a5,0xfffffffffffffffe
       a:   47a5                    li      a5,9
       c:   00e7d563                bge     a5,a4,0x16
      10:*  9002                    ebreak         <-- trapping instruction
            ...

    Code starting with the faulting instruction
    ===========================================
       0:   9002                    ebreak
            ...

As it is not always clear if the first 16 bits are at the start or in the
middle of a 32bit instruction it may become necessary to strip the first
u16 from the output before calling decodecode to get the correct
disassembled code.

Signed-off-by: Heinrich Schuchardt 
Reviewed-by: Bin Meng 
Reviewed-by: Sean Anderson

common: Drop asm/global_data.h from common header

2021-02-02T20:33:42+00:00

Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include  at all, so
remove that include.

Signed-off-by: Simon Glass 
Signed-off-by: Tom Rini

riscv: reset after crash

2020-12-14T07:16:41+00:00

If an exception occurs on ARM or x86, we call panic() which will try to
reset the board. Do the same on RISC-V.

To avoid -Werror=format-zero-length move a '\n' to the string passed to
panic. We don't need a message here as depending on CONFIG_PANIC_HANG we
will either see

    ### ERROR ### Please RESET the board ###

or

    resetting ...

as next message.

Reviewed-by: Rick Chen 
Signed-off-by: Heinrich Schuchardt