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<title>u-boot.git/arch/riscv/lib/rdtime.c, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>riscv: Rework riscv timer driver to only support S-mode</title>
<updated>2020-09-30T00:54:45+00:00</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2020-09-28T14:52:21+00:00</published>
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The riscv-timer driver currently serves as a shim for several riscv timer
drivers. This is not too desirable because it bypasses the usual timer
selection via the driver model. There is no easy way to specify an
alternate timing driver, or have the tick rate depend on the cpu's
configured frequency. The timer drivers also do not have device structs,
and so have to rely on storing parameters in gd_t. Lastly, there is no
initialization call, so driver init is done in the same function which
reads the time. This can result in confusing error messages. To a user, it
looks like the driver failed when trying to read the time, whereas it may
have failed while initializing.

This patch removes the shim functionality from the riscv-timer driver, and
has it instead implement the former rdtime.c timer driver. This is because
existing u-boot users who pass in a device tree (e.g. qemu) do not create a
timer device for S-mode u-boot. The existing behavior of creating the
riscv-timer device in the riscv cpu driver must be kept. The actual reading
of the CSRs has been redone in the style of Linux's get_cycles64.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
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<pre>
The riscv-timer driver currently serves as a shim for several riscv timer
drivers. This is not too desirable because it bypasses the usual timer
selection via the driver model. There is no easy way to specify an
alternate timing driver, or have the tick rate depend on the cpu's
configured frequency. The timer drivers also do not have device structs,
and so have to rely on storing parameters in gd_t. Lastly, there is no
initialization call, so driver init is done in the same function which
reads the time. This can result in confusing error messages. To a user, it
looks like the driver failed when trying to read the time, whereas it may
have failed while initializing.

This patch removes the shim functionality from the riscv-timer driver, and
has it instead implement the former rdtime.c timer driver. This is because
existing u-boot users who pass in a device tree (e.g. qemu) do not create a
timer device for S-mode u-boot. The existing behavior of creating the
riscv-timer device in the riscv cpu driver must be kept. The actual reading
of the CSRs has been redone in the style of Linux's get_cycles64.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: Implement riscv_get_time() API using rdtime instruction</title>
<updated>2018-12-18T01:56:27+00:00</updated>
<author>
<name>Anup Patel</name>
<email>anup@brainfault.org</email>
</author>
<published>2018-12-12T14:12:31+00:00</published>
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This adds an implementation of riscv_get_time() API that is using
rdtime instruction.

This is the case for S-mode U-Boot, and is useful for processors
that support rdtime in M-mode too.

Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</content>
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<pre>
This adds an implementation of riscv_get_time() API that is using
rdtime instruction.

This is the case for S-mode U-Boot, and is useful for processors
that support rdtime in M-mode too.

Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
</pre>
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</content>
</entry>
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