u-boot.git/arch/riscv/lib/sifive_cache.c, branch master Unnamed repository; edit this file 'description' to name the repository. driver: cache: Remove SiFive PL2 driver 2026-03-12T18:57:15+00:00 Nick Hu nick.hu@sifive.com 2026-01-19T05:55:23+00:00 61e2430360a592040357ab6a7241c29666b11e28 Under single core boot platform, the secondary cores won't enter the u-boot spl. Therefore we move the pl2 driver from u-boot to the Opensbi. Signed-off-by: Nick Hu <nick.hu@sifive.com> Signed-off-by: Jimmy Ho <jimmy.ho@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Under single core boot platform, the secondary cores won't enter the
u-boot spl. Therefore we move the pl2 driver from u-boot to the Opensbi.

Signed-off-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Jimmy Ho <jimmy.ho@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD 2024-10-11T17:44:47+00:00 Simon Glass sjg@chromium.org 2024-09-30T01:49:46+00:00 bef9fdbed2e525ce9264d2ae2fbcb37db7472052 Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org> 
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
riscv: cache: support cache enable in SPL stage 2023-12-27T09:28:57+00:00 Zong Li zong.li@sifive.com 2023-12-14T14:09:37+00:00 40c76dfed29ac2173bd32d730979ef2531029048 The power gating feature of pl2 should be enabled as early as possible, it would be better to put it in SPL stage. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
The power gating feature of pl2 should be enabled as early as possible,
it would be better to put it in SPL stage.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
riscv: Remove common.h usage 2023-10-24T20:34:45+00:00 Tom Rini trini@konsulko.com 2023-10-12T23:03:59+00:00 0b9441ae76db88b6871adc31b7e59355286f2847 We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> 
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
riscv: lib: implement enable_caches for sifive cache 2021-09-07T02:34:29+00:00 Zong Li zong.li@sifive.com 2021-09-01T07:01:41+00:00 213ed175b0a97313982c8341c34e48f0ea59b60e The enable_caches is a generic hook for architecture-implemented, we define this function to enable composable cache of sifive platforms. In sifive_cache, it invokes the generic cache_enable interface of cache uclass to execute the relative implementation in SiFive ccache driver. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com> 
The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.

In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>