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<title>u-boot.git/arch/riscv/lib/smp.c, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/riscv/lib/smp.c?h=main</id>
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<updated>2023-10-24T20:34:45Z</updated>
<entry>
<title>riscv: Remove common.h usage</title>
<updated>2023-10-24T20:34:45Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-10-12T23:03:59Z</published>
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<id>urn:sha1:0b9441ae76db88b6871adc31b7e59355286f2847</id>
<content type='text'>
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
</entry>
<entry>
<title>common: Drop linux/printk.h from common header</title>
<updated>2023-09-24T13:54:57Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-09-15T00:21:46Z</published>
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<id>urn:sha1:1e94b46f73cedcebbff73799203f3266c5b28d90</id>
<content type='text'>
This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h

Move this out of the common header and include it only where needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: core: Drop ofnode_is_available()</title>
<updated>2022-09-29T20:11:31Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-09-07T02:27:17Z</published>
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<id>urn:sha1:8909066199281b86bf4ee7673ec6d7983dd12a26</id>
<content type='text'>
This function is also available as ofnode_is_enabled(), so use that
instead.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>riscv: Introduce AVAILABLE_HARTS</title>
<updated>2022-09-26T06:29:13Z</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2022-09-21T06:34:54Z</published>
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<id>urn:sha1:e0465f80bd33f239612ee9f0ee7b6cf13d2f5b4d</id>
<content type='text'>
In SMP all harts will register themself in available_hart
during start up. Then main hart will send IPI to other harts
according to this variables. But this mechanism may not
guarantee that all other harts can jump to next stage.

When main hart is sending IPI to other hart according to
available_harts, but other harts maybe still not finish the
registration. Then the SMP booting will miss some harts finally.
So let it become an option and it will be enabled by default.

Please refer to the discussion:
https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>spl: introduce SPL_XIP to config</title>
<updated>2022-09-26T06:28:43Z</updated>
<author>
<name>Nikita Shubin</name>
<email>n.shubin@yadro.com</email>
</author>
<published>2022-09-02T08:47:39Z</published>
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<id>urn:sha1:c2bdf02c9d40da7154fea46b7d10343fe9f14209</id>
<content type='text'>
U-Boot and SPL don't necessary share the same location, so we might end
with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory.

In case of non XIP boot mode, we rely on such variables as "hart_lottery"
and "available_harts_lock" which we use as atomics.

The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL,
so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes.

This adds an option special for SPL to behave it in XIP manner and we don't
use hart_lottery and available_harts_lock, during start proccess.

Signed-off-by: Nikita Shubin &lt;n.shubin@yadro.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
</entry>
<entry>
<title>common: Drop asm/global_data.h from common header</title>
<updated>2021-02-02T20:33:42Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-10-31T03:38:53Z</published>
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<id>urn:sha1:401d1c4f5d2d29c4bc4beaec95402ca23eb63295</id>
<content type='text'>
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include &lt;asm/global_data.h&gt; at all, so
remove that include.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>riscv: Use a valid bit to ignore already-pending IPIs</title>
<updated>2020-09-30T00:54:52Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2020-09-21T11:51:37Z</published>
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<id>urn:sha1:f760c9a1fd485beae7612e39576e5fbf77c5d96b</id>
<content type='text'>
Some IPIs may already be pending when U-Boot is started. This could be a
problem if a secondary hart tries to handle an IPI before the boot hart has
initialized the IPI device.

To be specific, the Kendryte K210 ROM-based bootloader does not clear IPIs
before passing control to U-Boot. Without this patch, the secondary hart
jumps to address 0x0 as soon as it enters secondary_hart_loop, and then
hangs in its trap handler.

This commit introduces a valid bit so secondary harts know when and IPI
originates from U-Boot, and it is safe to use the IPI API. The valid bit is
initialized to 0 by board_init_f_init_reserve. Before this, secondary harts
wait in wait_for_gd_init.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Leo Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>riscv: Match memory barriers between send_ipi_many and handle_ipi</title>
<updated>2020-09-30T00:54:52Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2020-09-21T11:51:36Z</published>
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<id>urn:sha1:d4990a46485f2f6592ae29f2b822043dbdeae15d</id>
<content type='text'>
Without a matching barrier on the write side, the barrier in handle_ipi
does nothing. It was entirely possible for the boot hart to write to addr,
arg0, and arg1 *after* sending the IPI, because there was no barrier on the
sending side.

Fixes: 90ae281437 ("riscv: add option to wait for ack from secondary harts in smp functions")
Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Leo Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>riscv: Clean up IPI initialization code</title>
<updated>2020-07-01T07:01:22Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2020-06-24T10:41:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=40686c394e533fec765fe237936e353c84e73fff'/>
<id>urn:sha1:40686c394e533fec765fe237936e353c84e73fff</id>
<content type='text'>
The previous IPI code initialized the device whenever the first call was
made to a riscv_*_ipi function. This made it difficult to determine when
the IPI device was initialized. This patch introduces a new function
riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is
called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions
should be called.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
</entry>
<entry>
<title>riscv: add option to wait for ack from secondary harts in smp functions</title>
<updated>2019-12-10T00:23:10Z</updated>
<author>
<name>Lukas Auer</name>
<email>lukas.auer@aisec.fraunhofer.de</email>
</author>
<published>2019-12-08T22:28:51Z</published>
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<id>urn:sha1:90ae28143700bae4edd23930a7772899ad259058</id>
<content type='text'>
Add a wait option to smp_call_function() to wait for the secondary harts
to acknowledge the call-function request. The request is considered to
be acknowledged once each secondary hart has cleared the corresponding
IPI.

As part of the call-function request, the secondary harts invalidate the
instruction cache after clearing the IPI. This adds a delay between
acknowledgment (clear IPI) and fulfillment (call function) of the
request. We want to use the acknowledgment to be able to judge when the
request has been completed. Remove the delay by clearing the IPI after
cache invalidation and just before calling the function from the
request.

Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
Tested-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
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