u-boot.git/arch/riscv/lib, branch next

Merge patch series "bootm: Clean up arch-specific, pre-OS clean-up"

2026-03-19T00:36:50+00:00

Simon Glass  says:

Each arch does something slightly different before booting the OS. Some
archs even do different things depending on the CPU type.

It is quite hard to know what actually happens in the final milliseconds
before the OS boot.

This series attempts to start cleaning up U-Boot in this area.

The basic intent is to create a new bootm_final() function which can be
called by all archs. It provides some flags for a couple of necessary
variations but otherwise it is generic.

All architectures are converted over to use this new function.

board_quiesce_devices() is moved into bootm_final() so that all archs
benefit from it.

This series fixes a bug in device_remove() is fixed where removing a
parent with specialised flags (e.g. DM_REMOVE_ACTIVE_ALL) could leave
children activated, since they do not match the flags. This fixes is
needed to avoid bootm_final() causing test failures on sandbox.

Future work could take this a little further:
- Convert EFI loader to use the same function
- Improve comments for cleanup_before_linux() across architectures
- Support fake-run tracing on all archs

Link: https://lore.kernel.org/r/20260306023638.2678886-1-sjg@chromium.org

riscv: Call bootm_final()

2026-03-18T19:17:34+00:00

The RISC-V announce_and_cleanup() duplicates the common pre-boot
steps. Replace it with a call to bootm_final().

Move board_quiesce_devices() into bootm_final() so it is available to
all architectures. Drop the RISC-V weak definition and header
declaration since the generic one in bootm.h is used instead.

Signed-off-by: Simon Glass 
Reviewed-by: Tom Rini

driver: cache: Remove SiFive PL2 driver

2026-03-12T18:57:15+00:00

Under single core boot platform, the secondary cores won't enter the
u-boot spl. Therefore we move the pl2 driver from u-boot to the Opensbi.

Signed-off-by: Nick Hu 
Signed-off-by: Jimmy Ho 
Reviewed-by: Leo Yu-Chi Liang

RISC-V: implement private GCC library

2025-12-08T04:10:55+00:00

The following functions are provided:

Count leading zero bits

* int __clzsi2 (unsigned int a)
* int __clzdi2 (unsigned long a)
* int __clzti2 (unsigned long long a)

Count trailing zero bits

* int __ctzsi2 (unsigned int a)
* int __ctzdi2 (unsigned long a)
* int __ctzti2 (unsigned long long a)

Signed-off-by: Heinrich Schuchardt

spl: remove usage of CMD_BOOTx from image parsing

2025-11-03T17:52:05+00:00

Using CMD_* configs from spl doesn't make logical sense. Therefore
this patch replaces the checks for CMD_BOOTx with newly added library
symbols LIB_BOOT[IMZ] and SPL_LIB_BOOT[IMZ] which are enabled by their
respective CMD_* or SPL_* counterparts.

On platforms with non-secure falcon mode, SPL_BOOTZ is enabled by
default for 32-bit ARM systems and SPL_BOOTI is enabled by default for
64-bit ARM and RISCV.

The respective C files (image.c/zimage.c) are compiled based on library
symbols $(PHASE_)LIB_BOOTx instead which are in turn selected by both
CMD_BOOTx and SPL_BOOTx as required.

Signed-off-by: Anshul Dalal 
Reviewed-by: Tom Rini

arch/riscv/lib: update memmove and memcpy for big-endian

2025-08-14T07:33:00+00:00

Change the shift patterns for the unaligned memory move and copy code
to deal with big-endian by definign macros to change the shfit left and
right to go the opposite way.

Signed-off-by: Ben Dooks 
Reviewed-by: Leo Yu-Chi Liang

riscv: aclint_ipi: Support T-Head C900 CLINT

2025-07-03T08:14:13+00:00

Although timer component of the CLINT isn't fully compatible with the
generic RISC-V ACLINT, the IPI component behaves the same.

As the CLINT doesn't have corresponding riscv_aclint_timer driver
available, let's try looking for a compatible SYSCON device directly
when no riscv_aclint_timer device could be found on IPI initialization.

Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang

spl: Rename jump_to_image_no_args()

2025-06-13T19:22:53+00:00

This function is currently a misnomer at times as we have cases where it
passes arguments to the image. In preparation for making that be a more
common case rename this function to jump_to_image(...). In order to do
this, rename jump_to_image in board_init_r(...) to jumper so that we do
not have a conflict.

Signed-off-by: Simon Glass 
[trini: Reword the commit message, adding missing cases of
        jump_to_image_no_args()]
Signed-off-by: Tom Rini

Revert "booti/bootm: riscv: Verify image arch type"

2025-06-02T08:17:21+00:00

This reverts commit 37b0b22d8b7bbed6aa95b6daed06dcbf4a66f211 as
discussed in [1].

[1] https://lists.denx.de/pipermail/u-boot/2025-May/590841.html

Signed-off-by: Mayuresh Chitale 
Reviewed-by: Leo Yu-Chi Liang

riscv: lib: Split out support for T-Head cache management operations

2025-05-21T08:49:52+00:00

Designed before a standard set of cache management operations defined in
RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the
customized extension XTheadCMO, which has been used in the CV1800B port
of U-Boot.

This patch splits XTheadCMO-related code into a generic module, allowing
SoCs shipping T-Head cores to share the code.

Link: https://github.com/XUANTIE-RV/thead-extension-spec
Signed-off-by: Yao Zi 
Reviewed-by: Leo Yu-Chi Liang