<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/riscv, branch next</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/riscv?h=next</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/riscv?h=next'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2026-08-05T18:13:19Z</updated>
<entry>
<title>board: sophgo: add support for Milk-V Duo 256M</title>
<updated>2026-08-05T18:13:19Z</updated>
<author>
<name>Hiago De Franco</name>
<email>hfranco@baylibre.com</email>
</author>
<published>2026-07-23T14:44:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=98b59e181daa6c26d49f870fd58df8996b1cd7f1'/>
<id>urn:sha1:98b59e181daa6c26d49f870fd58df8996b1cd7f1</id>
<content type='text'>
Add U-Boot support for Milk-V Duo 256M.

This board has a different SoC compared to the Milk-V Duo 64M, it uses
the Sophgo SG2002 instead of the Sophgo CV1800B. Both SoCs share many
common IP blocks, so this board reuses the existing cv1800b CPU support.

The board shares the same 'board.c' with Milk-V Duo 64MB (CV1800B), so
use the same file for now.

Link: https://milkv.io/docs/duo/getting-started/duo256m
Signed-off-by: Hiago De Franco &lt;hfranco@baylibre.com&gt;
Acked-by: Leo Yu-Chi Liang &lt;leo.liang@sifive.com&gt;
</content>
</entry>
<entry>
<title>riscv: remove log_debug() in enable_caches()</title>
<updated>2026-07-27T02:39:22Z</updated>
<author>
<name>Charles Perry</name>
<email>charles.perry@microchip.com</email>
</author>
<published>2026-06-22T19:43:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b3b5b305e2c9f09440bda5fd3edf9e230c54d94f'/>
<id>urn:sha1:b3b5b305e2c9f09440bda5fd3edf9e230c54d94f</id>
<content type='text'>
log_debug() cannot be used before log_init() has been called. Remove the
log_debug() statement in enable_caches() since it is called before
log_init() in initcall_run_r().

This fixes a bug where a RISC-V system which does not have the "zicbom"
extension (such as PIC64-HPSC/HX) would get lost in an infinite loop in
log_dispatch().

Fixes: 9e859849e2ca ("riscv: cache: Add CBO instructions")
Signed-off-by: Charles Perry &lt;charles.perry@microchip.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;leo.liang@sifive.com&gt;
</content>
</entry>
<entry>
<title>riscv: Make RISCV_ACLINT visible</title>
<updated>2026-07-27T02:39:22Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2026-05-15T12:47:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0798f12031d0f5101e2dc05433e6d6984a610782'/>
<id>urn:sha1:0798f12031d0f5101e2dc05433e6d6984a610782</id>
<content type='text'>
A platform (like Xilinx Microblaze V) does not have an ACLINT (Advanced
Core Local Interruptor) hardware block.

Make RISCV_ACLINT and SPL_RISCV_ACLINT Kconfig symbols visible with
prompts.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Reviewed-by: Yao Zi &lt;me@ziyao.cc&gt;
</content>
</entry>
<entry>
<title>riscv: Skip riscv_cpu_setup() when CPU driver is disabled</title>
<updated>2026-07-27T02:39:21Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2026-05-11T08:31:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d8810e1d4f82b8064e4b9e0a52b352670d79ae06'/>
<id>urn:sha1:d8810e1d4f82b8064e4b9e0a52b352670d79ae06</id>
<content type='text'>
Building on commit c64fc632a86a ("riscv: cpu: Use CONFIG_IS_ENABLED(CPU)
instead of plain ifdef"), add an early return in riscv_cpu_setup() when
CONFIG_CPU is not enabled. This allows platforms to save code space in
SPL by disabling CONFIG_SPL_CPU.

Without this patch, building U-Boot with CONFIG_CPU=n and CONFIG_EVENT=y
is broken: riscv_cpu_setup() is registered as an EVT_DM_POST_INIT_F event
spy, and when the CPU uclass is unavailable uclass_find_first_device()
returns no device, so the function returns -ENODEV. That in turn makes
event_notify_null() in dm_init_and_scan() fail and triggers a boot hang
("initcall initf_dm() failed"). Returning 0 early avoids that failure.

The compiler's dead-code elimination combined with --gc-sections
removes the unreachable code and all associated static data,
achieving significant size reduction without preprocessor guards:

  spl/u-boot-spl:all -4332 spl/u-boot-spl:rodata -2872
  spl/u-boot-spl:text -1460

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Reviewed-by: Yao Zi &lt;me@ziyao.cc&gt;
</content>
</entry>
<entry>
<title>riscv: dts: cv18xx: fix spi node name</title>
<updated>2026-07-27T02:39:21Z</updated>
<author>
<name>Hiago De Franco</name>
<email>hfranco@baylibre.com</email>
</author>
<published>2026-04-30T19:35:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=40ea5423f9aaa5cc9c8364f96542a72e830113ce'/>
<id>urn:sha1:40ea5423f9aaa5cc9c8364f96542a72e830113ce</id>
<content type='text'>
Fix warning:
arch/riscv/dts/cv18xx.dtsi:208.26-216.5: Warning (spi_bus_bridge):
/soc/spi-nor@10000000: node name for SPI buses should be 'spi'

Signed-off-by: Hiago De Franco &lt;hfranco@baylibre.com&gt;
</content>
</entry>
<entry>
<title>riscv: binman: Always set default configuration in FIT image</title>
<updated>2026-07-21T09:16:02Z</updated>
<author>
<name>Raymond Mao</name>
<email>raymond.mao@riscstar.com</email>
</author>
<published>2026-05-20T10:45:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=eb7de3ccf1a12467b701b65f8e46af74744ec935'/>
<id>urn:sha1:eb7de3ccf1a12467b701b65f8e46af74744ec935</id>
<content type='text'>
When CONFIG_MULTI_DTB_FIT is enabled, the FIT image contains multiple
device tree configurations for different boards. The default
configuration must be explicitly set to ensure the FIT framework
traverses all available configurations instead of falling back to
CONFIG_DEFAULT_DEVICE_TREE.

Without this default property, fit_find_config_node() will use
CONFIG_DEFAULT_DEVICE_TREE as the configuration name to match.
This prevents the SPL from correctly selecting the appropriate
DTB based on runtime board detection (e.g., from EEPROM).

Remove the conditional guard so that "default = conf-1" is always
present in the FIT image, regardless of CONFIG_MULTI_DTB_FIT.

Signed-off-by: Raymond Mao &lt;raymond.mao@riscstar.com&gt;
Signed-off-by: Guodong Xu &lt;guodong@riscstar.com&gt;
</content>
</entry>
<entry>
<title>spl: k1: enable SPI NOR flash detection and boot</title>
<updated>2026-07-21T09:16:01Z</updated>
<author>
<name>Guodong Xu</name>
<email>guodong@riscstar.com</email>
</author>
<published>2026-05-20T10:45:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e63500cab0c04012a92f0e870339316408e2f7cf'/>
<id>urn:sha1:e63500cab0c04012a92f0e870339316408e2f7cf</id>
<content type='text'>
Add nor_early_init() to probe the QSPI controller and SPI NOR flash
in SPL.  Switch spl_boot_device() to BOOT_DEVICE_SPI so the board
boots from SPI flash.

Change the default device tree to k1-musepi-pro, whose u-boot
overlay already defines the QSPI controller and flash node with
bootph-pre-ram markers.  Enable the required SPI driver model and
flash config options.

Signed-off-by: Guodong Xu &lt;guodong@riscstar.com&gt;
</content>
</entry>
<entry>
<title>board: k1: enable pmic in spl</title>
<updated>2026-07-21T09:12:53Z</updated>
<author>
<name>Raymond Mao</name>
<email>raymond.mao@riscstar.com</email>
</author>
<published>2026-06-30T01:19:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=80aa3d316060a30777842c79d032376d425424d6'/>
<id>urn:sha1:80aa3d316060a30777842c79d032376d425424d6</id>
<content type='text'>
Add Spacemit P1 SoC support in SPL. And set the default voltage
for BUCKs and LDOs.

Also update MAINTAINERS: add Guodong Xu as co-maintainer, list the
u-boot-spacemit mailing list, register the new K1 driver files (i2c,
PMIC, regulator), and fix a pre-existing '@@' typo in Huan Zhou's
email.

Fixes: 1cd239f44438 ("riscv: spacemit: bananapi_f3: initial support added")
Signed-off-by: Raymond Mao &lt;raymond.mao@riscstar.com&gt;
Signed-off-by: Guodong Xu &lt;guodong@riscstar.com&gt;
Tested-by: Songsong Zhang &lt;sszhang@vsit.ai&gt;
</content>
</entry>
<entry>
<title>spacemit: k1: Add DDR firmware support to SPL</title>
<updated>2026-07-21T08:57:14Z</updated>
<author>
<name>Raymond Mao</name>
<email>raymond.mao@riscstar.com</email>
</author>
<published>2026-06-30T01:19:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=83026cf8f90b04ff02eede32cd646c2e961ccdbf'/>
<id>urn:sha1:83026cf8f90b04ff02eede32cd646c2e961ccdbf</id>
<content type='text'>
Include DDR initialization firmware in the SPL image. The firmware
path can be specified via the DDR_FW_FILE environment variable. If
the firmware is not found, an empty placeholder file is created to
allow the build to proceed without DDR initialization support.

Signed-off-by: Raymond Mao &lt;raymond.mao@riscstar.com&gt;
Signed-off-by: Guodong Xu &lt;guodong@riscstar.com&gt;
Tested-by: Songsong Zhang &lt;sszhang@vsit.ai&gt;
</content>
</entry>
<entry>
<title>spacemit: k1: add TLV EEPROM support in SPL</title>
<updated>2026-07-21T08:57:13Z</updated>
<author>
<name>Raymond Mao</name>
<email>raymond.mao@riscstar.com</email>
</author>
<published>2026-06-30T01:19:10Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b3ec88a7f391e57b1b5d67144844d34ac03fe1c3'/>
<id>urn:sha1:b3ec88a7f391e57b1b5d67144844d34ac03fe1c3</id>
<content type='text'>
And support for required components including clock, I2C controller,
and I2C EEPROM.

Signed-off-by: Raymond Mao &lt;raymond.mao@riscstar.com&gt;
Signed-off-by: Guodong Xu &lt;guodong@riscstar.com&gt;
Tested-by: Songsong Zhang &lt;sszhang@vsit.ai&gt;
</content>
</entry>
</feed>
