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<title>u-boot.git/arch/riscv, branch v2018.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/riscv?h=v2018.07</id>
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<updated>2018-05-29T06:45:04Z</updated>
<entry>
<title>riscv: dts: Support cfi flash</title>
<updated>2018-05-29T06:45:04Z</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2018-05-29T03:05:54Z</published>
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<id>urn:sha1:7286e46a790b0e007b4039b3d415a230d5ab84be</id>
<content type='text'>
Add nor node for cfi-flash driver and smc node
for smc(aftsmc020) controller.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Signed-off-by: Rick Chen &lt;rickchen36@gmail.com&gt;
Cc: Greentime Hu &lt;green.hu@gmail.com&gt;
</content>
</entry>
<entry>
<title>riscv: dts: Sync DT with Linux Kernel</title>
<updated>2018-05-29T06:45:03Z</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2018-05-29T02:53:41Z</published>
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<id>urn:sha1:c14e90e8445e7b1c3531b4bdeb778c47bd6570eb</id>
<content type='text'>
Use same dts to boot U-Boot and RISC-V
Linux Kernel v4.16-rc2 in ax25-ae350 platform.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Signed-off-by: Rick Chen &lt;rickchen36@gmail.com&gt;
Cc: Greentime Hu &lt;green.hu@gmail.com&gt;
</content>
</entry>
<entry>
<title>riscv: cpu: nx25: Rename as ax25</title>
<updated>2018-05-29T06:45:02Z</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2018-05-29T01:54:40Z</published>
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<id>urn:sha1:6f4dd62f338e327bf2135bc72f559e27d6cab54d</id>
<content type='text'>
Andes has rearranged the product combinations.
nx25 and ax25 both are RISC-V architecture cpu core.
But ax25 has MMU unit inside, and nx25 is not.

Cpu nx25 and platform ae250 are arranged in pairs.
Cpu ax25 and platform ae350 are arranged in pairs.

This patch will rename
nx25 as ax25
ae250 as ae350
nx25-ae250 as ax25-ae350
including filename, variable, string and definition.

Then u-boot can boot linux kernel in ae350
platform reasonably.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Signed-off-by: Rick Chen &lt;rickchen36@gmail.com&gt;
Cc: Greentime Hu &lt;green.hu@gmail.com&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert single license tags to Linux Kernel style</title>
<updated>2018-05-29T06:44:21Z</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2018-05-29T06:10:06Z</published>
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<id>urn:sha1:7215787c4ea4b14ed2efbc9926c7ea539294a151</id>
<content type='text'>
Fix license tags problem after apply patchs about
riscv: Enable efi_loader support.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Signed-off-by: Rick Chen &lt;rickchen36@gmail.com&gt;
Cc: Greentime Hu &lt;green.hu@gmail.com&gt;
</content>
</entry>
<entry>
<title>efi_loader: Enable RISC-V support</title>
<updated>2018-05-29T06:43:12Z</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2018-05-28T11:06:37Z</published>
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<id>urn:sha1:6836adbe753b241499430812ec5ef41ba61bdd83</id>
<content type='text'>
We have almost all pieces needed to support RISC-V UEFI binaries in place already.
The only missing piece are ELF relocations for runtime code and
data.

This patch adds respective support in the linker script and the runtime
relocation code. It also allows users to enable the EFI_LOADER configuration
switch on RISC-V platforms.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>riscv: Add board_quiesce_devices stub</title>
<updated>2018-05-29T06:43:12Z</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2018-04-23T05:59:46Z</published>
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<id>urn:sha1:b66babda459e3862230f147048a4c65419e81e07</id>
<content type='text'>
This patch adds an empty stub for board_quiesce_devices() which allows boards
to quiesce their devices before we boot into an OS in a platform agnostic way.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>riscv: Add EFI application infrastructure</title>
<updated>2018-05-29T06:43:12Z</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2018-04-23T05:59:45Z</published>
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<id>urn:sha1:493d1e88b676675e0c2a8614abcba0dcbb9befa4</id>
<content type='text'>
The hello world binary and a few selftests require to build EFI target
binaries, not just the EFI host environment.

This patch adds all required files to generate an EFI binary for
RISC-V.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>riscv: Enable function sections</title>
<updated>2018-05-29T06:43:12Z</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2018-04-23T05:59:44Z</published>
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<id>urn:sha1:6cc1a2af46c448e7d822fa4976a8d6e10fc5273b</id>
<content type='text'>
The linker can remove sections that are never addressed, so it makes a lot
of sense to declare every function as an individual section.

This reduces the output U-Boot code size by ~30kb for me.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>riscv: Add setjmp/longjmp code</title>
<updated>2018-05-29T06:43:12Z</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2018-04-23T05:59:43Z</published>
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<id>urn:sha1:a7f99e5dd7dfa1853dee25e0fcb761eee0fb3ad3</id>
<content type='text'>
To support efi_loader we need to have platform support for setjmp/longjmp.
Add it here.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>riscv: Define PLATFORM__CLEAR_BIT for generic_clear_bit()</title>
<updated>2018-05-16T01:44:05Z</updated>
<author>
<name>Bryan O'Donoghue</name>
<email>pure.logic@nexus-software.ie</email>
</author>
<published>2018-04-30T14:56:04Z</published>
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<id>urn:sha1:accdce5f86084be63eebc970532513f063115a8e</id>
<content type='text'>
riscv bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().

This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
riscv bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().

Signed-off-by: Bryan O'Donoghue &lt;pure.logic@nexus-software.ie&gt;
Cc: Rick Chen &lt;rick@andestech.com&gt;
Cc: Greentime Hu &lt;green.hu@gmail.com&gt;
</content>
</entry>
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