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<title>u-boot.git/arch/x86/cpu/Makefile, branch v2017.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu/Makefile?h=v2017.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu/Makefile?h=v2017.01'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2016-10-18T07:58:50Z</updated>
<entry>
<title>x86: Add implementations of setjmp() and longjmp()</title>
<updated>2016-10-18T07:58:50Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-10-18T02:29:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f822403f0164be74a5161b65698d0f01f4556234'/>
<id>urn:sha1:f822403f0164be74a5161b65698d0f01f4556234</id>
<content type='text'>
Bring in these functions from Linux v4.4. They will be needed for EFI loader
support.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add basic support for broadwell</title>
<updated>2016-03-17T02:27:25Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:18Z</published>
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<id>urn:sha1:2f3f477b77d3a528de41e52a8ba874fd47fb6513</id>
<content type='text'>
This adds the broadwell architecture, with the CPU driver and some useful
header files.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move cache-as-RAM code into a common location</title>
<updated>2016-03-17T02:27:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:06:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1223d737a38dab7f05e7d62a3c931e28aa1e1495'/>
<id>urn:sha1:1223d737a38dab7f05e7d62a3c931e28aa1e1495</id>
<content type='text'>
This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE</title>
<updated>2015-12-09T09:44:50Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-11-26T01:46:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9bf76c21e0248d06ad7e804b1a95d6cd0bc5f14f'/>
<id>urn:sha1:9bf76c21e0248d06ad7e804b1a95d6cd0bc5f14f</id>
<content type='text'>
NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Add a way to call 32-bit code from 64-bit mode</title>
<updated>2015-08-05T14:44:07Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-08-04T18:33:55Z</published>
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<id>urn:sha1:6f92ed8f1abfe94ee1c96c83c21f4092bb04ff63</id>
<content type='text'>
The procedure to drop from 64-bit mode to 32-bit is a bit messy. Add a
function to take care of it. It requires identity-mapped pages and that
the calling code is running below 4GB.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add support for U-Boot as an EFI application</title>
<updated>2015-08-05T14:44:06Z</updated>
<author>
<name>Ben Stoltz</name>
<email>stoltz@google.com</email>
</author>
<published>2015-08-04T18:33:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3dcdd17b43c5cfd3a216169948dfd08d6741c631'/>
<id>urn:sha1:3dcdd17b43c5cfd3a216169948dfd08d6741c631</id>
<content type='text'>
Add the required x86 glue code. This includes the initial start-up,
relocation and jumping to efi_main(). We also need to avoid fiddling with
interrupts.

Signed-off-by: Ben Stoltz &lt;stoltz@google.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add I/O APIC register access routines</title>
<updated>2015-07-15T00:03:17Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-23T04:18:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3d232878289bf59e83c6b152407a01f6e0fb790b'/>
<id>urn:sha1:3d232878289bf59e83c6b152407a01f6e0fb790b</id>
<content type='text'>
I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and version register offset are also added.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: dm: Clean up cpu drivers</title>
<updated>2015-07-15T00:03:15Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-12T06:52:20Z</published>
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<id>urn:sha1:be3f06bcc47e04bfc5fb7c900958918e2d019ef4</id>
<content type='text'>
This commit does the following to clean up x86 cpu dm drivers:
- Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated
  file arch/x86/cpu/cpu_x86.c
- Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent
  naming with other dm drivers
- Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly
  the same as the one in the intel baytrail cpu driver
- Update intel baytrail cpu driver to use cpu_x86_get_desc() and
  cpu_x86_bind()

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Refactor PIRQ routing support</title>
<updated>2015-06-04T08:39:39Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-05-25T14:35:04Z</published>
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<id>urn:sha1:9c7dea602edd9027848d312e9b3b69f06c15f163</id>
<content type='text'>
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Support QEMU x86 targets</title>
<updated>2015-06-04T08:39:38Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-05-07T13:34:08Z</published>
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<id>urn:sha1:a65b25d148fb0a9ef7dd5fba4ae2709f5bcae0c6</id>
<content type='text'>
This commit introduces the initial U-Boot support for QEMU x86 targets.
U-Boot can boot from coreboot as a payload, or directly without coreboot.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig
   https://patchwork.ozlabs.org/patch/479745/
</content>
</entry>
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