u-boot.git/arch/x86/cpu/coreboot/coreboot.c, branch v2014.04

Coding Style cleanup: remove trailing white space

2013-10-14T20:06:53Z

Signed-off-by: Wolfgang Denk

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38Z

Signed-off-by: Wolfgang Denk [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini

x86: Add coreboot timestamps

2013-05-13T20:33:22Z

Add selected coreboot timestamps into bootstage to get a unified view of the boot timings. Signed-off-by: Simon Glass

x86: Implement panic output for coreboot

2013-05-13T20:33:20Z

panic_puts() can be called in early boot to display a message. It might help with early debugging. Signed-off-by: Simon Glass Reviewed-by: Tom Wai-Hong Tam

x86: Permit bootstage and timer data to be used prior to relocation

2013-03-04T23:57:36Z

It is useful to be able to access the timer before U-Boot has relocated so that we can fully support bootstage. Add new global_data members to support this. Signed-off-by: Simon Glass

x86: drop unused code in coreboot.c

2012-12-06T22:30:44Z

The function setup_pcat_compatibility() is weak and implemented as empty function in board.c hence we don't have to override that with another empty function. monitor_flash_len is unused, drop it. Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass

x86: Provide a way to throttle port80 accesses

2012-12-06T22:30:43Z

Some systems (like Google Link device) provide the ability to keep a history of the target CPU port80 accesses, which is extremely handy for debugging. The problem is that the EC handling port 80 access is orders of magnitude slower than the AP. This causes random loss of trace data. This change allows to throttle port 80 accesses such that in case the AP is trying to post faster than the EC can handle, a delay is introduced to make sure that the post rate is throttled. Experiments have shown that on Link the delay should be at least 350,000 of tsc clocks. Throttling is not being enabled by default: to enable it one would have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild the u-boot image. With upcoming EC code optimizations this number could be decreased (new new value should be established experimentally). Signed-off-by: Vadim Bendebury Signed-off-by: Simon Glass

x86: Issue SMI to finalize Coreboot in final stage

2012-12-06T22:30:43Z

This will write magic value to APMC command port which will trigger an SMI and cause coreboot to lock down the ME, chipset, and CPU. Signed-off-by: Duncan Laurie Signed-off-by: Simon Glass

x86: Fix MTRR clear to detect which MTRR to use

2012-12-06T22:30:43Z

Coreboot was always using MTRR 7 for the write-protect cache entry that covers the ROM and U-boot was removing it. However with 4GB configs we need more MTRRs for the BIOS and so the WP MTRR needs to move. Instead coreboot will always use the last available MTRR that is normally set aside for OS use and U-boot can clear it before the OS. Signed-off-by: Duncan Laurie Signed-off-by: Simon Glass

x86: Emit port 80 post codes in show_boot_progress()

2012-12-06T22:30:43Z

This helps us monitor boot progress and determine where U-Boot dies if there are any problems. Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass