u-boot.git/arch/x86/cpu/coreboot/coreboot.c, branch v2016.01

x86: coreboot: Convert to use more dm drivers

2015-09-09T13:48:03Z

Move to driver model for RTC, USB and ETH on coreboot. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: qemu: Implement PIRQ routing

2015-06-04T09:03:18Z

Support QEMU PIRQ routing via device tree on both i440fx and q35 platforms. With this commit, Linux booting on QEMU from U-Boot has working ATA/SATA, USB and ethernet. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: coreboot: Control I/O port 0xb2 writing via device tree

2015-06-04T09:03:18Z

Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes U-Boot to hang on QEMU q35 target. We introduce a config option in the device tree "u-boot,no-apm-finalize" under /config node if we don't want to do that. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: coreboot: Fix cosmetic issues

2015-06-04T09:03:17Z

Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: config: Enable hook for saving MRC configuration

2015-01-24T13:13:45Z

Add a hook to ensure that this information is saved. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

x86: Add support for MTRRs

2015-01-13T15:25:00Z

Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. Clean up the existing header file to follow style, and remove the unneeded code. These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit). Signed-off-by: Simon Glass

x86: Remove board_early_init_r()

2014-11-25T13:33:59Z

This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

x86: Make show_boot_progress() common

2014-11-21T06:34:15Z

This function can probably be used on all x86 boards, so move it into the common file. Signed-off-by: Simon Glass

x86: Tidy up coreboot header usage

2014-11-21T06:34:13Z

There is no need to explicitly write 'arch-coreboot' when including headers, as when the arch directory points to coreboot the correct files will be used. Signed-off-by: Simon Glass

x86: Emit post codes in startup code for Chromebooks

2014-11-21T06:34:11Z

On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng