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<title>u-boot.git/arch/x86/cpu/coreboot/sdram.c, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu/coreboot/sdram.c?h=main</id>
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<updated>2026-06-25T00:13:24Z</updated>
<entry>
<title>treewide: move bi_dram[] from bd to gd</title>
<updated>2026-06-25T00:13:24Z</updated>
<author>
<name>Ilias Apalodimas</name>
<email>ilias.apalodimas@linaro.org</email>
</author>
<published>2026-06-17T07:48:19Z</published>
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<id>urn:sha1:1174c99ab421168221be372bd83a4143bf5f167d</id>
<content type='text'>
Currently, the bi_dram[] information is stored in the board info
structure (bd). Because bd is only valid after reserve_board(),
dram_init_banksize() must be called late in the initialization process.
This limitation is problematic, as it forces us to rely on a variety of
bespoke functions to determine board RAM, bank memory sizes, and other
early setup requirements.

By moving bi_dram[] into the global data (gd), we can run it earlier.
This is particularly convenient since boards define their own
dram_init_banksize() routines, which do not always rely on parsing
Device Tree (DT) memory nodes.

Additionally, U-Boot defaults to relocating to the top of the first memory
bank. While boards currently use custom functions to override this
behavior, having the DRAM bank information available earlier in gd makes
relocating to a different bank trivial and standardizes the process.

Reviewed-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Tested-by: Michal Simek &lt;michal.simek@amd.com&gt; # Versal Gen 2 Vek385
Tested-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
Tested-by: Christophe Leroy (CS GROUP) &lt;chleroy@kernel.org&gt;
</content>
</entry>
<entry>
<title>x86/coreboot: Exclude memory regions starting above 4GB</title>
<updated>2026-02-16T18:00:42Z</updated>
<author>
<name>Jeremy Compostella</name>
<email>jeremy.compostella@intel.com</email>
</author>
<published>2026-02-04T02:42:36Z</published>
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<id>urn:sha1:8666b16015d4212facacc514e2eb626f3630dcf0</id>
<content type='text'>
This commit updates the RAM region filtering logic in
board_get_usable_ram_top() to skip any memory regions whose start address
is above 4GB. Previously, only the end address was capped at 4GB, but
regions entirely above this threshold were still considered.

Typically, the following memory map entries would cause
board_get_usable_ram_top() to return 0x100000000, which is incorrect.

    start=00000000, end=00001000, type=16
    start=00001000, end=000a0000, type=1
    start=000a0000, end=000f6000, type=2
    start=000f6000, end=000f7000, type=16
    start=000f7000, end=00100000, type=2
    start=00100000, end=6f170000, type=1
    start=6f170000, end=70000000, type=16
    start=70000000, end=80800000, type=2
    start=e0000000, end=f8000000, type=2
    start=fa000000, end=fc000000, type=2
    start=fc800000, end=fc880000, type=2
    start=fd800000, end=fe800000, type=2
    start=feb00000, end=feb80000, type=2
    start=fec00000, end=fed00000, type=2
    start=fed20000, end=fed80000, type=2
    start=feda1000, end=feda2000, type=2
    start=fedc0000, end=fede0000, type=2
    start=100000000, end=102400000, type=2
    start=102400000, end=47f800000, type=1
    start=4000000000, end=4020000000, type=2

By adding a check to continue the loop if the region's start address
exceeds 0xffffffffULL, the function now properly ignores regions that are
not usable in 32-bit address space.

Signed-off-by: Jeremy Compostella &lt;jeremy.compostella@intel.com&gt;
</content>
</entry>
<entry>
<title>Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"</title>
<updated>2024-05-20T19:35:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-20T19:35:03Z</published>
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<id>urn:sha1:03de305ec48b0bb28554372abb40ccd46dbe0bf9</id>
<content type='text'>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""</title>
<updated>2024-05-19T14:16:36Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-19T02:20:43Z</published>
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<id>urn:sha1:d678a59d2d719da9e807495b4b021501f2836ca5</id>
<content type='text'>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>global: Make &lt;asm/global_data.h&gt; include &lt;asm/u-boot.h&gt;</title>
<updated>2024-05-06T21:07:48Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-01T02:40:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6a7185887b83a5cc334c7ce5bd65970381b2f4ce'/>
<id>urn:sha1:6a7185887b83a5cc334c7ce5bd65970381b2f4ce</id>
<content type='text'>
This follows the example of RISC-V where &lt;asm/global_data.h&gt; includes
&lt;asm/u-boot.h&gt; directly as "gd" includes a reference to bd_info already
and so the first must include the second anyhow. We then remove
&lt;asm/u-boot.h&gt; from all of the places which include references to "gd"
an so have &lt;asm/global_data.h&gt; already.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>x86: Remove &lt;common.h&gt; and add needed includes</title>
<updated>2024-05-06T21:05:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-04-27T14:10:56Z</published>
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<id>urn:sha1:e51478ba42687234c1b13720be8a6573cb17624e</id>
<content type='text'>
Remove &lt;common.h&gt; from all x86 architecture files and when needed add
missing include files directly.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>common: return type board_get_usable_ram_top</title>
<updated>2023-08-15T16:21:17Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2023-08-12T18:16:58Z</published>
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<id>urn:sha1:d768dd88552df18d4a0527cf3d6ddd05dc072f02</id>
<content type='text'>
board_get_usable_ram_top() returns a physical address that is stored in
gd-&gt;ram_top. The return type of the function should be phys_addr_t like the
current type of gd-&gt;ram_top.

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
</content>
</entry>
<entry>
<title>board_f: Fix types for board_get_usable_ram_top()</title>
<updated>2022-09-23T19:12:42Z</updated>
<author>
<name>Pali Rohár</name>
<email>pali@kernel.org</email>
</author>
<published>2022-09-09T15:32:40Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=049704f808d5e643668a33a76e55f925d4c1b36a'/>
<id>urn:sha1:049704f808d5e643668a33a76e55f925d4c1b36a</id>
<content type='text'>
Commit 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t")
changed type of ram_top member from ulong to phys_addr_t but did not
changed types in board_get_usable_ram_top() function which returns value
for ram_top.

So change ulong to phys_addr_t type also in board_get_usable_ram_top()
signature and implementations.

Fixes: 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t")
Signed-off-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Allow installing an e820 when booting from coreboot</title>
<updated>2021-03-27T02:04:29Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-03-15T05:00:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e7bae8283fea94cf470542916a063182c9e5771a'/>
<id>urn:sha1:e7bae8283fea94cf470542916a063182c9e5771a</id>
<content type='text'>
Move this code into a generic location so that it can be used by other x86
boards which want to boot from coreboot. Also ensure that this is called
if booting from coreboot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Make coreboot sysinfo available to any x86 board</title>
<updated>2021-03-27T00:59:37Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-03-15T05:00:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e35b6497f417c60cdcaa521eb4cbd3b2bb2e8336'/>
<id>urn:sha1:e35b6497f417c60cdcaa521eb4cbd3b2bb2e8336</id>
<content type='text'>
It is possible to boot U-Boot for chromebook_coral either 'bare metal' or
from coreboot. In the latter case we want to provide access to the coreboot
sysinfo tables. Move the definitions into a file available to any x86
board.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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