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<title>u-boot.git/arch/x86/cpu/coreboot, branch next</title>
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<updated>2026-06-25T00:13:24Z</updated>
<entry>
<title>treewide: move bi_dram[] from bd to gd</title>
<updated>2026-06-25T00:13:24Z</updated>
<author>
<name>Ilias Apalodimas</name>
<email>ilias.apalodimas@linaro.org</email>
</author>
<published>2026-06-17T07:48:19Z</published>
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<id>urn:sha1:1174c99ab421168221be372bd83a4143bf5f167d</id>
<content type='text'>
Currently, the bi_dram[] information is stored in the board info
structure (bd). Because bd is only valid after reserve_board(),
dram_init_banksize() must be called late in the initialization process.
This limitation is problematic, as it forces us to rely on a variety of
bespoke functions to determine board RAM, bank memory sizes, and other
early setup requirements.

By moving bi_dram[] into the global data (gd), we can run it earlier.
This is particularly convenient since boards define their own
dram_init_banksize() routines, which do not always rely on parsing
Device Tree (DT) memory nodes.

Additionally, U-Boot defaults to relocating to the top of the first memory
bank. While boards currently use custom functions to override this
behavior, having the DRAM bank information available earlier in gd makes
relocating to a different bank trivial and standardizes the process.

Reviewed-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Tested-by: Michal Simek &lt;michal.simek@amd.com&gt; # Versal Gen 2 Vek385
Tested-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
Tested-by: Christophe Leroy (CS GROUP) &lt;chleroy@kernel.org&gt;
</content>
</entry>
<entry>
<title>x86/coreboot: Exclude memory regions starting above 4GB</title>
<updated>2026-02-16T18:00:42Z</updated>
<author>
<name>Jeremy Compostella</name>
<email>jeremy.compostella@intel.com</email>
</author>
<published>2026-02-04T02:42:36Z</published>
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<id>urn:sha1:8666b16015d4212facacc514e2eb626f3630dcf0</id>
<content type='text'>
This commit updates the RAM region filtering logic in
board_get_usable_ram_top() to skip any memory regions whose start address
is above 4GB. Previously, only the end address was capped at 4GB, but
regions entirely above this threshold were still considered.

Typically, the following memory map entries would cause
board_get_usable_ram_top() to return 0x100000000, which is incorrect.

    start=00000000, end=00001000, type=16
    start=00001000, end=000a0000, type=1
    start=000a0000, end=000f6000, type=2
    start=000f6000, end=000f7000, type=16
    start=000f7000, end=00100000, type=2
    start=00100000, end=6f170000, type=1
    start=6f170000, end=70000000, type=16
    start=70000000, end=80800000, type=2
    start=e0000000, end=f8000000, type=2
    start=fa000000, end=fc000000, type=2
    start=fc800000, end=fc880000, type=2
    start=fd800000, end=fe800000, type=2
    start=feb00000, end=feb80000, type=2
    start=fec00000, end=fed00000, type=2
    start=fed20000, end=fed80000, type=2
    start=feda1000, end=feda2000, type=2
    start=fedc0000, end=fede0000, type=2
    start=100000000, end=102400000, type=2
    start=102400000, end=47f800000, type=1
    start=4000000000, end=4020000000, type=2

By adding a check to continue the loop if the region's start address
exceeds 0xffffffffULL, the function now properly ignores regions that are
not usable in 32-bit address space.

Signed-off-by: Jeremy Compostella &lt;jeremy.compostella@intel.com&gt;
</content>
</entry>
<entry>
<title>arch/x86/cpu: Call x86_cpu_reinit_f for 64-bits</title>
<updated>2025-04-04T18:26:35Z</updated>
<author>
<name>Jeremy Compostella</name>
<email>jeremy.compostella@intel.com</email>
</author>
<published>2025-03-18T17:40:03Z</published>
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<id>urn:sha1:e4246c1521c4b7bb1e3bece5c921f4c7e6a85e60</id>
<content type='text'>
As both CONFIG_X86_RUN_64BIT and X86_RUN_64BIT_NO_SPL cases run U-Boot
in 64-bit mode with the CPU fully initialized already.

Signed-off-by: Jeremy Compostella &lt;jeremy.compostella@intel.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arch/x86: Add 64-bit U-Boot configuration without SPL</title>
<updated>2025-04-04T18:26:35Z</updated>
<author>
<name>Jeremy Compostella</name>
<email>jeremy.compostella@intel.com</email>
</author>
<published>2025-03-18T17:39:40Z</published>
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<id>urn:sha1:1878c32c4d4790ab171d1ca9c8182627752fb59a</id>
<content type='text'>
This commit introduces a new configuration option X86_RUN_64BIT_NO_SPL
to allow building U-Boot as a 64-bit binary without using the SPL
(Secondary Program Loader). The motivation is to simplify the boot
process for certain x86-based platforms that do not require SPL, such as
those booting directly from a 64-bit coreboot firmware.

This update revises the `X86_RUN_64BIT` configuration to more accurately
describe its role as "32-bit SPL followed by 64-bit U-Boot." It
clarifies the sequence of operations during the boot process, where the
system transitions from a 32-bit SPL (Secondary Program Loader) to the
main 64-bit U-Boot.

Signed-off-by: Jeremy Compostella &lt;jeremy.compostella@intel.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: cpu: Use default print_cpuinfo() for all</title>
<updated>2024-10-18T20:10:22Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2024-10-05T19:11:57Z</published>
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<id>urn:sha1:c222dda2da1283a859533c0cacca975f86524dc6</id>
<content type='text'>
Most of the copies of the print_cpuinfo() call the default method.
Remove all of those in order to have only the default one when
no `cpu` command is compiled.

This also helps avoiding compiler warning, e.g.:

  arch/x86/cpu/tangier/tangier.c:23:5: warning: no previous prototype for ‘print_cpuinfo’ [-Wmissing-prototypes]

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Add timestamps from coreboot to bootstage</title>
<updated>2024-10-18T20:10:21Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-08-28T20:13:54Z</published>
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<id>urn:sha1:e1c0dd369d759e1dc23e2cd7ab9fca2095c9b714</id>
<content type='text'>
Receiving timestamps from coreboot was unceremoniously dropped some time
ago. Add it back.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Fixes: 8ad01ce36f7 ("x86: Remove x86 specific GD flags as they are...")
</content>
</entry>
<entry>
<title>x86: coreboot: Update the timestamp code to use sysinfo</title>
<updated>2024-10-18T20:10:21Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-08-28T20:13:53Z</published>
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<id>urn:sha1:734b0cbbca62a70d5a7c40d17fc45eb6cf1298ea</id>
<content type='text'>
Rather than using a special variable, get the timestamp info from the
coreboot sysinfo struct. Return a proper error as well.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Make default_print_cpuinfo be a weak alias for print_cpuinfo</title>
<updated>2024-10-18T20:10:21Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-01-22T14:35:12Z</published>
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<id>urn:sha1:b84d2f203edb102568cd63630394559d62d51737</id>
<content type='text'>
While a few SoCs have a unique print_cpuinfo function, a number of them
just use default_print_cpuinfo. Make default_print_cpuinfo have a weak
alias to provie print_cpuinfo.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD</title>
<updated>2024-10-11T17:44:47Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-09-30T01:49:46Z</published>
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<id>urn:sha1:bef9fdbed2e525ce9264d2ae2fbcb37db7472052</id>
<content type='text'>
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"</title>
<updated>2024-05-20T19:35:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-20T19:35:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=03de305ec48b0bb28554372abb40ccd46dbe0bf9'/>
<id>urn:sha1:03de305ec48b0bb28554372abb40ccd46dbe0bf9</id>
<content type='text'>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
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