u-boot.git/arch/x86/cpu/coreboot, branch v2015.01

Replace with

2014-12-08T14:35:46Z

Including is enough for general use. Signed-off-by: Masahiro Yamada

x86: Remove board_early_init_r()

2014-11-25T13:33:59Z

This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

Merge git://git.denx.de/u-boot-x86

2014-11-24T17:00:00Z

Conflicts: arch/x86/cpu/Makefile Signed-off-by: Tom Rini

x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory

2014-11-23T11:49:02Z

The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile are redundant because the build system descends into the directory only when CONFIG_SYS_COREBOOT is defined. Signed-off-by: Masahiro Yamada Cc: Simon Glass Acked-by: Simon Glass

linux/kernel.h: sync min, max, min3, max3 macros with Linux

2014-11-23T11:48:30Z

U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada Acked-by: Pavel Machek Acked-by: Lukasz Majewski Tested-by: Lukasz Majewski [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini

x86: Make show_boot_progress() common

2014-11-21T06:34:15Z

This function can probably be used on all x86 boards, so move it into the common file. Signed-off-by: Simon Glass

x86: Tidy up coreboot header usage

2014-11-21T06:34:13Z

There is no need to explicitly write 'arch-coreboot' when including headers, as when the arch directory points to coreboot the correct files will be used. Signed-off-by: Simon Glass

x86: Refactor PCI to permit alternate init

2014-11-21T06:34:11Z

We want access PCI earlier in the init sequence, so refactor the code so that it does not require use of a BSS variable to work. This will allow us to use early malloc() to store information about a PCI hose. Common PCI code moves to arch/x86/cpu/pci.c and a new board_pci_setup_hose() function is provided by boards to set up the (single) hose used by that board. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

x86: Emit post codes in startup code for Chromebooks

2014-11-21T06:34:11Z

On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

x86: Add chromebook_link board

2014-11-21T06:34:11Z

This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass