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<title>u-boot.git/arch/x86/cpu/coreboot, branch v2015.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu/coreboot?h=v2015.04</id>
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<updated>2015-01-24T13:13:45Z</updated>
<entry>
<title>x86: config: Enable hook for saving MRC configuration</title>
<updated>2015-01-24T13:13:45Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-01-20T05:16:15Z</published>
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<id>urn:sha1:069f5481ba19b819ef11ba23181a264fc566b180</id>
<content type='text'>
Add a hook to ensure that this information is saved.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Use ipchecksum from net/</title>
<updated>2015-01-24T13:13:44Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-01-20T05:16:09Z</published>
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<id>urn:sha1:b18c68d8918095672b295aef7bfbfc466b82c710</id>
<content type='text'>
The existing IP checksum function is only accessible to the 'coreboot' cpu.
Drop it in favour of the new code in the network subsystem.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Configure pci memory regions</title>
<updated>2015-01-13T15:25:05Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-01-06T14:14:23Z</published>
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<id>urn:sha1:cdcc17d73dcbc40ccc74af98d914fbd61df4b85e</id>
<content type='text'>
Configure coreboot pci memory regions so that pci device drivers
could work correctly.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig</title>
<updated>2015-01-13T15:25:03Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-01-06T14:14:18Z</published>
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<id>urn:sha1:9d74f03460a788e004fb1fb4cb53003d26f57298</id>
<content type='text'>
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.

Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Set up timer base correctly</title>
<updated>2015-01-13T15:25:02Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-01-06T14:14:13Z</published>
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<id>urn:sha1:5c564b0d2fd108ebc5fd6bb0081b981ee32ddf0b</id>
<content type='text'>
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.

Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Add support for MTRRs</title>
<updated>2015-01-13T15:25:00Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-01-01T23:18:07Z</published>
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<id>urn:sha1:aff2523f6998dca1f667aa0d26cc8f351c5628dc</id>
<content type='text'>
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.

Clean up the existing header file to follow style, and remove the unneeded
code.

These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Replace &lt;compiler.h&gt; with &lt;linux/compiler.h&gt;</title>
<updated>2014-12-08T14:35:46Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-11-26T07:00:58Z</published>
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<id>urn:sha1:afc366f01bea2361bc08b1a7b51e0cef81d66173</id>
<content type='text'>
Including &lt;linux/compiler.h&gt; is enough for general use.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
</entry>
<entry>
<title>x86: Remove board_early_init_r()</title>
<updated>2014-11-25T13:33:59Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-11-15T01:18:22Z</published>
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<id>urn:sha1:65990d568074ad878cbc7e4eb1053508e3707cb6</id>
<content type='text'>
This function is not needed. Remove it to improve the generic init sequence
slightly.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-x86</title>
<updated>2014-11-24T17:00:00Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2014-11-24T17:00:00Z</published>
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<id>urn:sha1:746667f1e56bf08d03e66a178df3c4f4f6c806e1</id>
<content type='text'>
Conflicts:
	arch/x86/cpu/Makefile

Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory</title>
<updated>2014-11-23T11:49:02Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-11-13T03:28:41Z</published>
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<id>urn:sha1:37c9940a09d582bb90eed4e59110c388c90f2bf8</id>
<content type='text'>
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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