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<title>u-boot.git/arch/x86/cpu/coreboot, branch v2015.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu/coreboot?h=v2015.07</id>
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<updated>2015-06-04T09:03:18Z</updated>
<entry>
<title>x86: qemu: Implement PIRQ routing</title>
<updated>2015-06-04T09:03:18Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-03T01:20:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5c564226fc8948e435edea8eb8c5c4afbc5edef1'/>
<id>urn:sha1:5c564226fc8948e435edea8eb8c5c4afbc5edef1</id>
<content type='text'>
Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Control I/O port 0xb2 writing via device tree</title>
<updated>2015-06-04T09:03:18Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-03T01:20:05Z</published>
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<id>urn:sha1:f2653e8dd92229328480da35c26e6f9fbfec4381</id>
<content type='text'>
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree "u-boot,no-apm-finalize" under /config node if we don't want
to do that.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Fix cosmetic issues</title>
<updated>2015-06-04T09:03:17Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-03T01:20:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=65cdd9be3e0fe79909962bba9bedf7967d44d60b'/>
<id>urn:sha1:65cdd9be3e0fe79909962bba9bedf7967d44d60b</id>
<content type='text'>
Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: link: Add PCH driver to support SPI Flash</title>
<updated>2015-04-30T00:51:50Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-04-20T13:07:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=87f4cd3a308b0bcffd8f9b5e7121fdb086c080f5'/>
<id>urn:sha1:87f4cd3a308b0bcffd8f9b5e7121fdb086c080f5</id>
<content type='text'>
U-Boot on coreboot does not have a driver for the PCH so cannot see the
SPI peripheral now that it has moved inside the PCH. Add a simple driver so
that SPI flash works again.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: x86: pci: Convert coreboot to use driver model for pci</title>
<updated>2015-04-18T17:11:09Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-03-05T19:25:32Z</published>
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<id>urn:sha1:801f4f1bbc5ae838cdd50df09895dc275726d23a</id>
<content type='text'>
Move coreboot-x86 over to driver model for PCI.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Support machines with &gt;4GB of RAM</title>
<updated>2015-04-17T01:27:40Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-03-02T19:40:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=892ff8e972efc7d4f42750e4fdbb2c2fefb78229'/>
<id>urn:sha1:892ff8e972efc7d4f42750e4fdbb2c2fefb78229</id>
<content type='text'>
Some systems have more than 4GB of RAM. U-Boot can only place things below
4GB so any memory above that should not be used. Ignore any such memory so
that the memory size will not exceed the maximum.

This prevents gd-&gt;ram_size exceeding 4GB which causes problems for PCI
devices which use DMA.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Lukasz Majewski &lt;l.majewski@samsung.com&gt;
</content>
</entry>
<entry>
<title>x86: config: Enable hook for saving MRC configuration</title>
<updated>2015-01-24T13:13:45Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-01-20T05:16:15Z</published>
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<id>urn:sha1:069f5481ba19b819ef11ba23181a264fc566b180</id>
<content type='text'>
Add a hook to ensure that this information is saved.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Use ipchecksum from net/</title>
<updated>2015-01-24T13:13:44Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-01-20T05:16:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b18c68d8918095672b295aef7bfbfc466b82c710'/>
<id>urn:sha1:b18c68d8918095672b295aef7bfbfc466b82c710</id>
<content type='text'>
The existing IP checksum function is only accessible to the 'coreboot' cpu.
Drop it in favour of the new code in the network subsystem.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Configure pci memory regions</title>
<updated>2015-01-13T15:25:05Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-01-06T14:14:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cdcc17d73dcbc40ccc74af98d914fbd61df4b85e'/>
<id>urn:sha1:cdcc17d73dcbc40ccc74af98d914fbd61df4b85e</id>
<content type='text'>
Configure coreboot pci memory regions so that pci device drivers
could work correctly.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig</title>
<updated>2015-01-13T15:25:03Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-01-06T14:14:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9d74f03460a788e004fb1fb4cb53003d26f57298'/>
<id>urn:sha1:9d74f03460a788e004fb1fb4cb53003d26f57298</id>
<content type='text'>
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.

Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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