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<title>u-boot.git/arch/x86/cpu/coreboot, branch v2016.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu/coreboot?h=v2016.03</id>
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<updated>2016-01-24T04:07:17Z</updated>
<entry>
<title>dm: x86: spi: Convert ICH SPI driver to driver model PCI API</title>
<updated>2016-01-24T04:07:17Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-19T03:19:21Z</published>
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<id>urn:sha1:f2b85ab5e6a91e29c1d64304be371753d75ed172</id>
<content type='text'>
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.

In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.

While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.

Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.

This patch includes Bin's fix-up patch from here:

   https://patchwork.ozlabs.org/patch/569478/

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Convert to use driver model timer</title>
<updated>2015-12-01T13:26:35Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-11-13T08:11:22Z</published>
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<id>urn:sha1:80af39842e64a44258ab5eb913659e29fc319903</id>
<content type='text'>
Convert all x86 boards to use driver model tsc timer.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Convert to use more dm drivers</title>
<updated>2015-09-09T13:48:03Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-08-28T09:22:38Z</published>
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<id>urn:sha1:5bc60d5a44d8603923784b5cee400b6dbf2624c6</id>
<content type='text'>
Move to driver model for RTC, USB and ETH on coreboot.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Allow &gt;=4GiB memory bank size</title>
<updated>2015-08-26T14:54:07Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-08-13T07:29:11Z</published>
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<id>urn:sha1:a25bc78e2f8d9f91c6f7d97a3d4a6632bec3c400</id>
<content type='text'>
Some platforms may have &gt;=4GiB memory, so we need make U-Boot report
such configuration correctly when booting as the coreboot payload.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Remove calculate_relocation_address()</title>
<updated>2015-08-26T14:54:07Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-08-13T07:29:10Z</published>
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<id>urn:sha1:c17ca6b5cd7158b63a78c4944c732c49dce8454f</id>
<content type='text'>
Now that we have generic routine to calculate relocation address,
remove the x86 specific one which is now only used by coreboot.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Correctly report E820 types</title>
<updated>2015-08-26T14:54:07Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-08-13T07:29:09Z</published>
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<id>urn:sha1:52b778603b7017885d67428c9cca9807bc6e2f7d</id>
<content type='text'>
coreboot has some extensions (type 6 &amp; 16) to the E820 types.
When we detect this, mark it as E820_RESERVED.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: pci: Tidy up the generic x86 PCI driver</title>
<updated>2015-07-15T00:03:19Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-07-04T00:28:25Z</published>
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<id>urn:sha1:945cae79e1b547d6edcce53aae68be2e3679a364</id>
<content type='text'>
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: qemu: Implement PIRQ routing</title>
<updated>2015-06-04T09:03:18Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-03T01:20:06Z</published>
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<id>urn:sha1:5c564226fc8948e435edea8eb8c5c4afbc5edef1</id>
<content type='text'>
Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Control I/O port 0xb2 writing via device tree</title>
<updated>2015-06-04T09:03:18Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-03T01:20:05Z</published>
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<id>urn:sha1:f2653e8dd92229328480da35c26e6f9fbfec4381</id>
<content type='text'>
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree "u-boot,no-apm-finalize" under /config node if we don't want
to do that.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Fix cosmetic issues</title>
<updated>2015-06-04T09:03:17Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-03T01:20:02Z</published>
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<id>urn:sha1:65cdd9be3e0fe79909962bba9bedf7967d44d60b</id>
<content type='text'>
Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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